%% Use uvmbuild to generate UVM Test Bench
% 
% Copyright 2019 The MathWorks, Inc.

%% Simulink Model Structure
% This example uses a Simulink(R) model, that includes these three
% subsystems.
%
% * A sequence subsystem, which generates stimulus for the DUT.
% * A DUT subsystem, which represents your HDL design. 
% * A scoreboard subsystem, which collects the outputs and checks them.
% In this example the DUT is a simple delay block.
%%
open_system('hdlv_uvmbuild');

%% Generate UVM Test Bench
% Generate a UVM test bench from this Simulink model, specifying the paths
% to the DUT, sequence, and scoreboard subsystems.
%%
%   uvmbuild('hdlv_uvmbuild/DUT','hdlv_uvmbuild/Sequence','hdlv_uvmbuild/Scoreboard');

%% Observe Generated Output
%
% The |uvmbuild| function creates a directory named
% |hdlv_uvmbuild_uvmbuild| containing the |uvm_testbench| directory. The
% |uvm_testbench| directory includes these
% subdirectories.
%
% * The |top| directory includes a SystemVerilog top module and generated scripts to
% execute in your HDL simulation environment.
% * The |DPI_dut| directory contains the SystemVerilog-DPI behavioral DUT.
% * The |sequence| directory contains the generated sequence transaction
% type and a UVM sequencer,
% which drives the transaction to the DUT.
% * The |scoreboard| directory contains the generated UVM scoreboard.
% * The |uvm_artifacts| directory contains UVM components, such as monitors, drivers, and agents, required for the UVM
% environment.

%% Run Generated UVM Test Bench
%
% # Start Modelsim(R) or Questasim in GUI mode.
% # In the HDL simulator, navigate to the top directory: 
% |cd hdlv_uvmbuild_uvmbuild\uvm_testbench\top\|
% # In the HDL simulator, enter this command to run your
% simulation: 
% |do run_tb_mq.do|



