%% Getting Started with Customizing Generated SystemVerilog Code
% This example shows you how to customize the generated SystemVerilog code
% in the SystemVerilog DPI Component Generation process. 

% Copyright 2013-2014 The MathWorks, Inc.

%% Requirements and Prerequisites
% Products required for this example:
%
% * MATLAB(R)
% * Simulink(R)
% * Simulink Coder(TM)
% * Mentor Graphics(R) ModelSim(R)/QuestaSim(R)
% * One of the supported C compilers: Microsoft(R) Visual C++, or GNU GCC

%% Background
% If the default generated SystemVerilog code does not meet your
% requirements, you have the option to customize the generated code. This
% example shows how to customize the generated code.
%
% In the following Simulink model the generated code corresponding to
% subsystems, F0, F2, F3, and F4, are exported separately as SystemVerilog
% modules. By default, each module contains three control signals: clock,
% clock enable, and reset. In HDL simulation, the subsystem update and
% output functions will be called on the rising edge of the clock signal.
% An event scheduler would trigger those update and output function in HDL
% simulator in the same sequence as in Simulink model. 


%% Open Example
% Run the following code to open the design
%
%   open_system('svdpi_SimpleFeedBack');
%
% <<../svdpi_simplefeedback_model.png>>
%
% <<../svdpi_simplefeedback_scope.png>>
%

%% Set Up Model for Code Generation
%
% Open the Simulink Model Configuration Parameter panel from the
% svpid_SimpleFeedBack model. Set the following parameters:
%
% Select Code Generation -> System Target File. Click Browse button and
% select "systemverilog_dpi_grt.tlc".
%
% In Toolchain setting, select one of the Visual Studio versions if you are
% using Windows, or one of the GCC toolchains if you are using Linux.
% Make sure that option "Generate code only" is unchecked. 
%
% Select Code Generation -> SystemVerilog DPI, and check the option
% "Customize generated SystemVerilog code". Make sure that "Source file
% template" is set to default template "svdpi_event.vgt". 
%
% You can also click the "Edit" button to view the default SystemVerilog
% template. 
%
% Now we are done with the Configuration Parameter panel. Click "OK" button
% to close it. 
%

%% Generate SystemVerilog DPI Component
%
% In the "svdpi_SimpleFeedBack" model, generate C code for subsystems F0, F2, F3, and
% F4. You can generate C code from the command-line by run the following
% commands in MATLAB:
%
%   rtwbuild('svdpi_SimpleFeedBack/F0')
%   rtwbuild('svdpi_SimpleFeedBack/F2')
%   rtwbuild('svdpi_SimpleFeedBack/F3')
%   rtwbuild('svdpi_SimpleFeedBack/F4')
%
% Now the C code for those subsystems are generated in subdirectories
% "F0_build", "F2_build", "F3_build" and "F4_build", respectively. 
%
%% Test Bench Files
%
% In the testbench "SimpleFeedback_tb.sv" the control signal is connected so that it flows from
% modules with higher execution order in Simulink to modules with lower
% execution order in Simulink.
%
%% Run the Generated Test Bench
%
% * Start ModelSim/QuestaSim in GUI mode and change the directory to the
% current directory in MATLAB. In ModelSim/QuestaSim, enter the following
% command to compile your design
%
%   do  build.do
%
% * In ModelSim/QuestaSim, enter the following command to simulate your
% design
%
%   do  sim.do
%
% When simulation finishes, you can exam the difference between the output
% of each subsystem and the captured signal in ModelSim's waveform window.
