%% Partly Serial Systolic FIR Filter Implementation
% This example shows how to implement a 32-tap lowpass FIR filter using the 
% <docid:dsp_ref.bvi0_ng-1 Discrete FIR Filter HDL Optimized> block.
%
% Both filter blocks in the example model implement an identical partly-
% serial 32-tap filter. The top block configures the serial filter
% by specifying the number of cycles, _N_ , between input samples. This spacing 
% allows each multiplier to be shared by _N_ coefficients. The second block 
% is configured to use a certain number of multipliers, _M_. These two
% configurations result in the same filter implementation. For 32 symmetric
% coefficients, there are 16 unique coefficients. Therefore the filter 
% shares each of 2 multipliers between 8 coefficients. 
%
% The model shows two ways of applying input samples, depending on the rate
% of the rest of your design. 
%% Open the Model
% Open the model. Inspect the top block parameters. The *Filter structure* is 
% set to |Partly serial systolic| and *Specify serialization factor as* is set to 
% |Minimum number of cycles between valid input samples|. The *Number of 
% cycles* is set (to 8) using a variable, _numCycles_. In the lower block, 
% *Specify serialization factor as* is set to |Maximum number of multipliers|. 
% The *Number of multipliers* is set (to 2) using a variable. The variables
% are defined in the |PostLoadFcn| callback function. 
% 
% From the color coding, you can see the rate of both filter blocks
% is the same, while the rate of the generated input samples is different. 
sys = 'PartlySerialSys32TapFilterHDL';
load_system(sys)
set_param(sys,'SimulationCommand','Update')
open_system(sys)

%% Run the Model and Inspect Results
% Run the model. Observe the input and output signals in the generated
% plots. The code to generate the plots is in the |PostSimFcn| callback. 
%
% <<../PartlySerialSys32TapFilterHDL_Input.png>>
%
% <<../PartlySerialSys32TapFilterHDL_Output.png>>
%
% From the model toolbar, open the *Logic Analyzer*. If the button is 
% not displayed, expand the *Review Results* app gallery. 
%
% <<../PartlySerialSys32TapFilterHDL_LA_menu.png>>
%
% Inspect the rising edges of |ready|, |validIn|,
% and |validOut|.
%
% <<../PartlySerialSys32TapFilterHDL_LA.png>>
%
%% Generate HDL Code
% To generate HDL code from either Discrete FIR Filter HDL Optimized block,
% right-click the block and select *Create Subsystem from Selection*. Then
% right-click the subsystem and select *HDL Code* > *Generate HDL Code for
% Subsystem*. Both blocks generate the same HDL code. 

%%  
% Copyright 2012 The MathWorks, Inc.