 %% Downsample a Signal
% Convert a signal from 48 kHz to 32 kHz using the FIR Rate Conversion HDL
% Optimized block.
%
% The source is a cosine input signal, sampled at 48kHz. The model passes a
% new data sample into the block on every time step by holding 
% |validIn| = |true|. After resampling, the |validOut| signal is |true| on 
% only 2/3 of the time steps.

%% Open the Model
sys = 'FIRRateConversionHDL_decim';
load_system(sys)
set_param(sys,'SimulationCommand','Update')
open_system(sys)

%% Configure the Model
% Define the data rate parameters in the |InitFcn| callback. 
%
% <<../FIRRCHDL_decim_InitFcn.png>>
%
% Configure the FIR Rate Conversion HDL Optimized block. Use the default 
% interpolation factor of 2 and decimation factor of 3. Use the |firmpm| 
% function to design an equiripple FIR filter. In the *Data Types* group, 
% set the *Coefficients* data type to |fixdt(1,16,15)| to 
% accommodate the filter you designed. 

%% Run the Model and Display Results
% Run the model. Use the *Logic Analyzer* to view the input and output 
% signals of the block. The blue icon in the model indicates streamed signals. 
% Launch the Logic Analyzer from the model's toolbar.
% 
% <<../analyzebuttondownarrow.png>>
%
% In the Logic Analyzer, note the pattern of |validIn| and the resulting 
% |validOut| signal. 
%
% <<../FIRRCHDL_decim_LASignals.png>>

%% Generate HDL Code
% To generate HDL code from the FIR Rate Converter HDL Optimized block, 
% right-click the block and select *Create Subsystem from Selection*. Then 
% right-click the subsystem and select *HDL Code* > *Generate HDL Code for Subsystem*.


%% 
% Copyright 2012 The MathWorks, Inc.