%% Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules
% This example shows how to synthesize and generate FPGA bitstream from a
% Simscape(TM) half-wave rectifier model and download the bitstream to 
% a Speedgoat FPGA I/O 334-325K target for Hardware-in-the-Loop (HIL) 
% implementation.

% Copyright 2018-2020 The MathWorks, Inc.

%% Hardware-in-the-Loop Workflow
%
% # Generate a HDL implementation model from the Simscape model by using 
% the Simscape HDL Workflow Advisor. The HDL implementation model is a
% Simulink(R) model that replaces the Simscape algorithm with HDL-compatible
% blocks
% # Generate FPGA bitstream for the HDL implementation model by using the 
% HDL Workflow Advisor
% # Download the bitstream to the Speedgoat FPGA I/O module by using the
% Simulink Real-Time Explorer for Hardware-in-the-Loop Simulation.

%% Half Wave Rectifier Model
% Open the Simscape half wave rectifier model. In the MATLAB(R) command prompt,
% enter:
ModelName = 'sschdlexHalfWaveRectifierExample';
open_system(ModelName)
set_param(ModelName, 'SimulationCommand', 'update');
%%
open_system([ModelName, '/Simscape_system'])
%%
% The half-wave rectifier consists of a Resistor, which is a linear block,
% and a Diode, which is a switched linear block. At the input and
% output port interfaces, the model has Simulink-PS Converter and
% PS-Simulink Converter blocks. The solver settings are configured for
% compatibility with Simscape HDL Workflow Advisor. If you open the 
% Block Parameters dialog box for the Solver Configuration block, 
% *Use local solver* is selected and |Backward Euler| is specified as the 
% *Solver type*. See <docid:hdlcoder_ug#mw_72877fb2-f383-4930-94af-48d17147d6e1>.
%
% To see the algorithm functionality, simulate the model.
sim(ModelName)
open_system([ModelName, '/Scope'])
%% 
% 2. Configure the Simscape Model for HDL compatibility by using the
% |hdlsetup| function:
%
%   hdlsetup('sschdlexHalfWaveRectifierExample')

%% Generate HDL Implementation Model
% To generate the HDL implementation model:
%
% 1. Open the Simscape HDL Workflow Advisor:
%
%   sschdladvisor('sschdlexHalfWaveRectifierExample')
%
% 2. To compare functionality of the HDL implementation model with the 
% original Simscape algorithm, select the *Generate implementation model* 
% step, and then select the *Generate valiadtion logic for the
% implementation model* check box. Use a *Validation logic tolerance* of
% |0.001|. Right-click the *Generate implementation model* step and select
% *Run to Selected Task*.
%
% The Advisor generates an HDL implementation model and a state-space
% validation model. To compare functionality of the HDL implementation model 
% with the original Simscape algorithm, open and simulate the state-space
% validation model. The output of this model matches the original Simscape 
% model. For a more systemic verification, see
% <docid:hdlcoder_ug#mw_0366f2ea-94dd-4b68-9dad-4ca41d92b7dc>.
%
% See also <docid:hdlcoder_ug#mw_b8157227-3515-480d-bc20-06288b9bee2f>.

%% Setup and Configuration
% The Speedgoat IO334-325K FPGA module uses Xilinx(R) Vivado(R) and
% _IP Core Generation_ workflow infrastructure. Before you deploy the HDL 
% implementation model on the Speedgoat IO module:
%
% 1. *Install Xilinx Vivado and Setup Tool Path*
%
% Install the latest version of Xilinx(R) Vivado(R) as listed in 
% <docid:hdlcoder_gs#btp_jaq>. Then, set the tool path to the installed 
% Xilinx Vivado executable by using the <docid:hdlcoder_ref#burmn3j-1> function.
%
%   hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2019.2\bin\vivado.bat')
%%
% 2. *Install Speedgoat Library and Speedgoat - HDL Coder Integration
% Packages*
%
% Install the Speedgoat Library and the Speedgoat - HDL Coder Integration
% packages. See <https://www.speedgoat.com/help/hdlcoder/page/refentry_workflow 
% Install Speedgoat HCIP>.
%
% 3. *Setup I/O Module*
%
% For real-time simulation, set up the I/O module. See
% <https://www.speedgoat.com/help/page/configuration/refentry_host_software_installation#refsect1_xilinx_hdl_software
% Xilinx HDL Software for Speedgoat I/O Hardware>.
% 
%% HDL Workflow Advisor
% The HDL Workflow Advisor guides you through HDL code generation and the 
% FPGA design process. Use the Advisor to:
%
% * Check the model for HDL code generation compatibility and
%  fix incompatible settings.
% * Generate HDL code, test bench, and scripts to build and run the
% code and test bench.
% * Perform synthesis and timing analysis.
% * Deploy the generated code on SoCs, FPGAs, and Speedgoat I/O modules.
%
% To open the HDL Workflow Advisor,use the 
% <docid:hdlcoder_ref#bsgdu85> function.
%
%    hdladvisor('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/Simscape_system/HDL Subsystem')
%
%%
% The left pane contains folders that represent a group of related 
% tasks. Expanding the folders and selecting a task displays 
% information about that task in the right pane. The right pane
% can contain simple controls for running the task to advanced parameters 
% and option settings that control code and test bench generation. 
% To learn more about each task, right-click that task, and select *What's This?*. 
% See <docid:hdlcoder_ug#bse5hm4>.

%% Generate FPGA Bitstream for Speedgoat Platform
%
% 1. Open the HDL implementation model, and then open the HDL Workflow Advisor 
% for the implementation model.
%%
%    open_system('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx')
%    hdladvisor('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/HDL Subsystem')
%
%%
% 2. In *Set Target Device and Synthesis Tool* task, specify *Target workflow* 
% as |Simulink Real-Time FPGA I/O| and *Target platform* as |Speedgoat
% IO334-325K|.
%
% <<sschil_set_target_device_synth_tool.png>>
%
% 3. In the *Set Target Reference Design* task, select a value of |x4| for the
% parameter |PCIe lanes|, and select *Run This Task*.
% 
% 4. In *Set Target Interface* task, map the input and output |single| data type ports
% to |PCIe Interface| and select *Run This Task*.
%
% <<sschil_set_target_interface.png>>
%
% 5. In the *Set Target Frequency* task, set the *Target Frequency (MHz)* 
% as |100|. 
%
% 6. Right-click the *Generate Simulink Real-Time Interface* task and 
% select *Run to Selected Task* to generate the HDL IP core, FPGA bitstream, 
% and download the bitstream onto the Speedgoat IO334 target. 
%
% A Simulink Real-Time Interface model is generated, and named as 
% *gm_gmStateSpaceHDL_sschdlexHalfWaveRectifierEx_slrt*.
%
% <<sschil_generatedslrtmodel.png>>
%
% For rapid prototyping, you can export the Workflow Advisor settings to
% a script. The script is a MATLAB file that you run from the command 
% line. You can modify and run the script, or import the settings into the 
% HDL Workflow Advisor User Interface. To save the workflow, in the HDL 
% Workflow Advisor User Interface, select *File > Export to Script*. 
% Save the file as |hdlworkflow_slrt_IO334.m|. 
%
% To import this file, in the HDL Workflow Advisor User Interface, select
% *File > Import from Script*. In the Import Workflow Configuration 
% dialog box, select the |hdlworkflow_slrt_IO334.m| file. 
% The HDL Workflow Advisor updates the tasks according to the imported
% script. See <docid:hdlcoder_ug#bu0ogdm-1>.

%% Deploy Bitstream to Speedgoat IO334-325k Target
%
% 1. *Connect Development Computer to Target*
%
% Connect the development computer to the target by using a cross-over 
% network cable. The Speedgoat Target IP address is
% |10.10.10.15|. Set the IP address of the communication link 
% between the development computer and target computer to a value
% |10.10.10.12| because the communication link must be in the same network.
%
% 2. *Setup and Configure Simulink Real-Time Explorer*
%
% You download the bitstream by using the Simulink Real-Time Explorer. To
% open the Simulink Real-Time Explorer, enter the command |slrtExplorer|.
% Alternatively, you can open the Explorer from the *REAL-TIME* tab of the 
% Simulink Toolstrip.
%
%   slrtExplorer
%
% a. In the *TARGET* pane click the *Add Target* button, and then click
% the *Properties* button on the toolbar. In the *Target Properties* 
% Workspace, click *Host-to-Target Communication*.
%
% * Set *IP Address* as |10.10.10.15|, *Port* as |22222|, *Subnet mask* as 
% |255.255.255.0|, and *Gateway* as |10.10.10.10|. 
% * Set *Target driver* as |Auto| and *Bus type* as |PCI|.
%
% b. In the *Target Properties* Workplace, click *Target Settings.
%
% * Select *USB Support* and *Graphics mode*.
% * Click *Boot Configuration* in *Target Properties* workspace.
% * Select *Boot mode* as |Network| and click on *Create boot disk*. The 
% Target MAC address appears in the *MAC address* field.
%
% Save the configuration by clicking the *save* button. 
%
% 3. *Create Real-Time Application*
%
% Open the Simulink Real-Time Interface model. Add a Scope block to the 
% model and connect it to the outputs. Log the output signals to view the 
% simuation results on the Simulation Data Inspector.
%
% <<sschil_slrtmodel.png>>
%
% 4. *Build and Run Real-Time Application*
%
% Click the *Run on Target* button on the *REAL_TIME* tab to compile and 
% download the model onto Speedgoat IO334-325k target.
%
% A target object name |tg| is created in the MATLAB workspace and the 
% model is run on the target. Observe the output simulation results
% on the Simulation Data Inspector. The simulation results of the 
% downloaded model match the original Simscape model simulation. 