%% Using Altera DSP Builder Advanced Blockset with HDL Coder
% This example shows how to use the Altera(R) DSP Builder Advanced Blockset with HDL
% Coder(TM).

% Copyright 2011-2016 The MathWorks, Inc.

%% Introduction
% Using the Altera(R) DSP Builder Advanced Blockset Subsystem block,
% or DSPBA Subsystem block, enables you to model
% designs using blocks from both Simulink(R) and Altera(R), and to
% automatically generate integrated HDL code. HDL Coder(TM) generates HDL code
% from the Simulink(R) blocks, and uses Altera(R) DSP Builder to generate
% HDL code from the DSPBA Subsystem blocks.
%
% In this example, the design, or code generation subsystem, contains two parts:
% one with Simulink(R) native blocks, and one with Altera(R) DSP Builder Advanced
% blocks. The Altera(R) blocks are grouped in a DSPBA Subsystem
% (hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem). Altera(R) DSP Builder 
% optimizes these blocks for Altera(R) FPGAs. In the rest of the design,
% Simulink(R) blocks and HDL Coder(TM) offer many model-based design
% features, such as distributed pipelining and delay balancing, to
% perform model-level optimizations.
%
%   open_system('hdlcoder_sldspba');
%   open_system('hdlcoder_sldspba/SLandDSPBA');
%
% <<hdlcoder_sldspba_toplevels.png>> 


%% Setup for Altera(R) DSP Builder Advanced Blockset 
% In order to use the Altera(R) DSP Builder Advanced Blockset Subsystem block,
% you must have Altera(R) Quartus II set up with Simulink(R). For version
% compatibility, please refer to the HDL Coder
% <matlab:helpview(fullfile(docroot,'hdlcoder/gs/language-and-tool-version-support.html')) documentation>.
%
      
%% Create Altera(R) DSP Builder Advanced Blockset Subsystem
% To create a DSPBA Subsystem:
%
% # Put the Altera(R) blocks in one subsystem and set its architecture to "Module"
% (the default value). 
% # Place a Device block at the top level of the subsystem. You can
% have subsystem hierarchy in a DSPBA Subsystem, but
% there must be a Device block at the top level of the hierarchy.
%
%   open_system('hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem');
%
% <<hdlcoder_sldspba_dspbadut.png>> 

%% Simulink(R) Components
% In this example, a Stateflow chart generates the channel and valid signals to drive the DSPBA subsystem.
%   
%   open_system('hdlcoder_sldspba/SLandDSPBA/Simulink Subsystem');
%
% <<hdlcoder_sldspba_sldut.png>>

%% Generate HDL Code
% You can use either makehdl at the command line or HDL Workflow Advisor to generate HDL code. To use makehdl: 
%
%   makehdl('hdlcoder_sldspba/SLandDSPBA');
%
% You can also generate a testbench, simulate, and synthesize the design as you would for any other model.

%% Handle Simulation Mismatch When Valid Signal Not Asserted
% The DSPBA Subsystem simulation may not match its
% generated code's behavior when the valid signal is not asserted under
% certain circumstances, such as when the folding option in both
% hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelIn 
% and hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelOut are turned on.
% The mismatch affects the downstream Simulink design and causes a test
% bench simulation failure.
%
% To see the mismatch, you can turn the folding setting on the ChannelIn and ChannelOut blocks:
%
%   set_param('hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelIn', 'FoldingEnabled', 1);
%   set_param('hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelOut', 'FoldingEnabled', 1);
%
% Then, generate the HDL code and test bench again:
%
%   makehdl('hdlcoder_sldspba/SLandDSPBA');
%   makehdltb('hdlcoder_sldspba/SLandDSPBA');
%
% After simulating the generated code and test bench,
% you can see that the outputs from HDL coder match the reference data only
% when the valid signal is asserted.
% 
% <<hdlcoder_sldspba_simulationmismatch.png>> 
%
% As the message from the test bench indicates, the mismatch is expected. 
%
% To avoid this simulation mismatch, insert an enabled subsystem at the DSPBA Subsystem output
% signals, before they reach the Simulink part of your design or the output ports of
% the overall design. The following subsystem shows how to connect signals
% to the enabled subsystem.
%
%   open_system('hdlcoder_sldspba/SLandDSPBA2');
%
% <<hdlcoder_sldspba_sldspbadut2.png>> 

displayEndOfDemoMessage(mfilename)
