%% Asynchronous FIFO Design in HDL Coder(TM)
% This example shows how to design and test an asynchronous FIFO in HDL Coder.

%   Copyright 2016 The MathWorks, Inc.

%% Introduction
% Simulink(TM) is a synchronous system simulator. But, it can be used to model
% and generate HDL code for an asynchronous FIFO design.  The example model
% implements a 64-element FIFO and is built as a self-testing model.
% 
% The FIFO input runs at a faster rate than its output. The data source in the
% model shifts in a well-defined sequence of values, controlled by a 'Full'
% output from the model. The model is self-checking, using a subsystem to
% compare the output data time series and an assertion block to confirm the
% correct output.

open_system('hdlcoder_asynchronous_fifo');
open_system('hdlcoder_asynchronous_fifo/FIFODUT');
set_param('hdlcoder_asynchronous_fifo', 'SimulationCommand', 'update');

%% Supporting Asynchronous Rate Transitions
% Simulink, being synchronous, cannot directly model an asynchronous
% transition. However, we can use the HDL Coder Black Box Encaspulated
% Documentation feature to allow the generated HDL Code to support asynchronous
% rate transitions. This feature allows the user to mark a Subsystem as using a
% Black Box implementation and then provide the associated HDL code directly
% inside the Subsystem. This feature is used at several different locations
% inside the Dual Rate FIFO in this model. In this model, the Rate Transition is
% simply replaced by a wire in the HDL code stored in the text block. Note that
% this code does not match the timing of the Simulink implementation that it is
% replacing.

open_system('hdlcoder_asynchronous_fifo/FIFODUT/DualRateFIFO/PushController/ClockCrossing/BitCrossing/VHDLImpl')
makehdl('hdlcoder_asynchronous_fifo/FIFODUT')

%% Validating the Asynchronous Implementation
% The HDL Code generated for this model cannot be successfully validated using
% HDL Coder's test bench generator or via the standard cosimulation model. This
% is because the behavior of the replacement code in the Black Box Encaspulated
% Documentation implementation does not match the timing of the blocks that it
% is substituting for. HDL Verifier's cosimulation capability can still be used
% to validate the HDL implementation within Simulink. It requires creating a
% custom model and then configuring the cosimulation block by hand. The
% Simulation tab specifies the clock, enable, and reset timing needed to drive
% the HDL code.

open_system('hdlcoder_asynchronous_fifo_tb')
open_system('hdlcoder_asynchronous_fifo_tb/FIFODUT_mq')

%% The Custom Cosimulation Model
% The verification model uses the self-checking Simulink testbench for
% confirming correctness. The original model remains in place, and a ModelSim
% Cosimulation block is placed in parallel to it. The Simulink self checking
% test bench must be duplicated to stimulate the cosimulation block and to
% validate its outputs in the same fashion that it does for the original
% Simulink model.



%% Simulating the Custom Cosimulation Model
% Once the cosimulation model is built and configured, it can be executed in the
% same fashion that an automatically generated cosimulation model is. First,
% ModelSim is launched by double clicking on the cyan block labelled "Start
% Simulator". This initiates communication between Simulink and ModelSim,
% compiles the HDL code and, and adds the user-selected signals to the ModelSim
% waveform window. Once ModelSim is ready, running the Simulink simulation will
% cosimulate with ModelSim and the self-checking testbench confirms the correct
% behavior of the Asynchronous HDL FIFO implementation.


displayEndOfDemoMessage(mfilename)
