ROI Selector

Select a region of interest (ROI) from pixel stream

Library:
Vision HDL Toolbox / Utilities

Description

The ROI Selector block selects a portion of the active frame from a video stream. The size of the inactive frame remains the same. The output control signals indicate a new active region of the frame. This diagram shows the inactive pixel regions in blue and the requested output region outlined in orange.

Specified region of the input frame returned as a pixel stream with pixels outside of the region marked as inactive.

You can specify a fixed size and location for the ROI, or you can select the region location dynamically by using an input port. You can select more than one region. Define each region by specifying its upper-left corner coordinates and dimensions. By default, the block returns one set of pixels and control signals for each region you specify. The block sets the inactive pixels in the output frame to zero.

Regions are independent from each other, so they can overlap. If you specify a region that includes the edge of the active frame, the block returns only the active portion of the region. This diagram shows the output frames for three requested regions. The second output region does not include the inactive area above the image.

Three regions (one partially falling outside of the active frame, and one overlapping another), returned as three pixel streams.

The block also provides a mode for vertical reuse. In this mode, you must specify regions that have no vertical overlap and are aligned in columns. Each column of regions shares one output pixel stream. The control signals define each region in the stream. This arrangement enables parallel processing of each column, and the reuse of downstream processing logic for each region in a column. To use this mode, select the Reuse output ports for vertically aligned regions parameter. Use the visionhdlframetoregions function to divide a frame into tiled regions for vertical reuse.

Eight tiled regions returned as two output pixel streams that each contain four vertically-aligned regions.

Ports

This image shows the additional ports on the block when you configure three regions of interest from input ports.

ROI Selector block with optional ports.

This block uses a streaming pixel interface with a pixelcontrol bus for frame control signals. This interface enables the block to operate independently of image size and format. All Vision HDL Toolbox™ blocks use the same streaming interface. The block accepts and returns a scalar pixel value and a bus that contains five control signals. The control signals indicate the validity of each pixel and its location in the frame. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

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`pixel` — Single image pixel
scalar

Single image pixel in a pixel stream, specified as a scalar that represents grayscale intensity.

double and single data types are supported for simulation, but not for HDL code generation.

`ctrl` — Control signals associated with pixel stream
`pixelcontrol` bus

Specify a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

`region1,...,regionN` — Region of interest
four-element row vector

Region of interest, specified as a row vector of four positive integers that define the coordinates of the top-left corner and dimensions of each desired output frame. The vector must have the form [hPos vPos hSize vSize]. The block has N region ports, where N is the Number of regions parameter value.

Dependencies

To enable this port, clear the Reuse output ports for vertically aligned regions parameter and set the Regions source parameter to Input port.

Output

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`pixel1,...,pixelN` — Output pixel
scalar

Output pixel, returned as a scalar value. The output data type is the same data type as the input pixel port. By default, the block has N output pixel ports, where N is the Number of regions parameter, or the number of rows in the Regions parameter matrix.

When you select Reuse output ports for vertically aligned regions, the block has one output pixel port for each column of vertically-aligned regions.

`ctrl1,...,ctrlN` — Control signals
`pixelcontrol` bus

Control signals, returned as a pixelcontrol bus that contains five signals. By default, the block has N output ctrl ports, where N is the Number of regions parameter, or the number of rows in the Regions parameter matrix.

When you select Reuse output ports for vertically aligned regions, the block has one output ctrl port for each column of aligned regions.

Data Types: bus

Parameters

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`Reuse output ports for vertically aligned regions` — Option to return one pixel stream for each column of regions
`off` (default) | `on`

When you select this parameter, you must specify regions that have no vertical overlap and that are aligned in columns. The block has one output pixel stream for each column of regions. This arrangement enables parallel processing of each column, and the reuse of downstream processing logic for each region in a column. Use the visionhdlframetoregions function to divide a frame into tiled regions for vertical reuse.

Dependencies

To enable this parameter, set the Regions source parameter to Property.

`Regions source` — Location of output region definitions
`Property` (default) | `Input port`

Specify the location of the output region definitions. You can set Regions source to one of these values:

Property — Specify the regions by using the Regions parameter.
Input port — Specify the regions by using input ports. Each input port corresponds to one region. The block samples the region input ports when vStart is true in the input control bus.

Dependencies

To enable this parameter, clear the Reuse output ports for vertically aligned regions parameter.

`Regions` — Rectangular ROIs to select from input frame
N-by-4 matrix

Specify rectangular ROIs to select from the input frame as an N-by-4 matrix.

N is the number of regions. The four elements that define each region are the top-left starting coordinates and the dimensions of the region and must be of the form [hPos vPos hSize vSize]. The coordinates count from the upper-left corner of the active frame, defined as [1,1]. hSize must be greater than 1.

When you clear the Reuse output ports for vertically aligned regions parameter, the regions can overlap, and N must not be greater than 16.

When you select Reuse output ports for vertically aligned regions, the regions in this matrix must have no vertical overlap and be aligned in columns. This diagram shows two examples of invalid regions outlined with a blue dashed line. The region on the left overlaps another region vertically. The two regions at the bottom do not align with the other regions in their columns. The regions do not have to cover the entire frame. Pixels outside of the tiled regions are marked as inactive pixels. The number of columns must not be greater than 16.

Dependencies

To enable this parameter, set the Regions source parameter to Property.

`Number of regions` — Number of region input ports
integer in the range [1, 16]

Specify the number of region input ports as an integer in the range [1, 16].

Dependencies

To enable this parameter, set the Regions source parameter to Input port.

Model Examples

Select Region of Interest

Select a region of active frame from a video stream by using the ROI Selector block from the Vision HDL Toolbox™.

Select Regions for Vertical Reuse

Divide a frame into tiled regions of interest (ROIs) and use those regions to configure the ROI Selector block for vertical reuse.

Algorithms

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The generated HDL code for the ROI Selector block uses two 32-bit counters. The block does not use additional counters for additional regions.

Latency

The block has a latency of three cycles.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

ROI Selector

Description