Pixel Stream Aligner

Align two streams of pixel data

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  • Library:

  • Vision HDL Toolbox / Utilities

  • Pixel Stream Aligner block

Description

The Pixel Stream Aligner block synchronizes two pixel streams by delaying one stream to match the timing of a reference stream. Many Vision HDL Toolbox™ algorithms delay the pixel stream, and the amount of delay can change as you adjust algorithm parameters. You can use this block to align streams for overlaying, comparing, or combining two streams such as in a Gaussian blur operation. Connect the delayed stream to the refPixel and refCtrl input ports, and the earlier stream to the pixel and ctrl input ports.

This waveform diagram shows the input streams, pixelIn and refPixelIn, and their associated control signals. The reference input frame starts later than the pixelIn frame. The output signals show that the block delays pixelIn to match the reference stream, and that both output streams share control signals. The waveform shows the short latency between the input refCtrl and the output refCtrl. In this simulation, to accommodate the delay of four lines between the input streams, the Maximum number of lines parameter must be set to at least 4.

Ports

This block uses a streaming pixel interface with a pixelcontrol bus for frame control signals. This interface enables the block to operate independently of image size and format. All Vision HDL Toolbox blocks use the same streaming interface. The block accepts and returns a scalar pixel value and a bus that contains five control signals. The control signals indicate the validity of each pixel and its location in the frame. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

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For single pixel streaming, specify pixel as a scalar intensity value, a row vector of Number of components values. For multipixel streaming, specify pixel as a column vector of Number of pixels pixel intensity values. This block does not support multipixel-multicomponent streaming.

Because the block delays this pixel stream to match the control signals of the reference stream, refPixel, pixel must be the earlier of the two streams.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | double | single

Specify a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

For multipixel streaming, each vector of pixel values has one set of control signals. Because the vector has only one valid signal, the pixels in the vector must be either all valid or all invalid. The hStart and vStart signals apply to the pixel with the lowest index in the vector. The hEnd and vEnd signals apply to the pixel with the highest index in the vector.

Data Types: bus

Specify refPixel as a scalar intensity value, a row vector of Number of components values, or a column vector of Number of pixels pixel intensity values. This block does not support multipixel-multicomponent streaming.

The allowed dimensions for refPixel depend on the dimensions of the input pixel stream. The Number of pixels must be the same.

Input pixel DimensionsAllowed refPixel Dimensions
1-by-11-by-1 or 1-by-3
1-by-31-by-1 or 1-by-3
4-by-14-by-1
8-by-18-by-1

Because the block delays the pixel input stream to match the reference control signals, refPixel must be the later of the two streams. The reference data and its control signals pass through the block with a small delay.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | double | single

Specify a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

For multipixel streaming, each vector of pixel values has one set of control signals. Because the vector has only one valid signal, the pixels in the vector must be either all valid or all invalid. The hStart and vStart signals apply to the pixel with the lowest index in the vector. The hEnd and vEnd signals apply to the pixel with the highest index in the vector.

The block uses these control signals for the aligned output stream.

Data Types: bus

Output

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The timing of the output pixel stream matches the timing of the output refPixel stream. The dimensions and data type of the output pixel stream match the input pixel stream.

The dimensions and data type of the output refPixel stream match the input refPixel stream. The block passes this stream through the block unchanged.

The block passes the input refCtrl signals through the block with a small delay.

Parameters

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Choose a power of two that accommodates the number of active pixels in a horizontal line. If you specify a value that is not a power of two, the block uses the next largest power of two. The block implements a circular buffer of 2M pixels, where M is Maximum number of lines + log2(Line buffer size).

The block implements a circular buffer of 2M pixels, where M is Maximum number of lines + log2(Line buffer size), and a line address buffer of Maximum number of lines locations. The circular memory stores the earlier input lines until the reference control signals arrive. The line address buffer stores the address of the start of each line. When the reference control signals arrive, the block uses the stored address to read and send the delayed line. This parameter must accommodate the difference in timing between the two input streams, including the internal latency before the block reads the first line. During simulation, the block warns when an overflow occurs. To avoid the overflow condition, increase Maximum number of lines. The delay between streams cannot exceed an entire frame.

When the input pixel is a vector, the block replicates the circular buffer for each element of the vector. In that case, the buffers use inputVectorSize×2M memory locations. The line address buffer remains the same size.

Model Examples

Harris Corner Detection

Harris Corner Detection

Use edge detection as the first step in corner detection. The algorithm is suitable for FPGAs. For another corner detection algorithm for FPGAs, see the FAST Corner Detector example.

Algorithms

The block stores the data from the pixel input port to a circular buffer and then reads the lines out to align with the reference control signals. The block also stores the address of the start of each line. To match the added processing delay of the buffer data path, the block delays the reference pixel data and control signals for around 10 cycles.

The diagram shows the architecture of the block. The RAM Circular Buffer is a memory of 2M pixels, where M is Maximum number of lines + log2(Line buffer size). The Line Address Buffer has Maximum number of lines locations. If the number of ctrl.Hstart assertions before the first refCtrl.Hstart assertion is greater than the size of the Line Address Buffer, the block overwrites both buffers and corrupts the output. In this diagram, Maximum number of lines is four, so four locations exist to store a line address in the buffer. The Frame Start Buffer is a single location to store ctrl.Vstart. The delay between the two streams must be less than the time between frame starts.

When the input pixel is a vector, the block replicates the RAM Circular Buffer for each element of the vector.

Extended Capabilities

See Also

Blocks

Objects

Introduced in R2017a

Vision HDL Toolbox Documentation

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