Check Input Resolution

Check that input signal has specified resolution

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  • Library:

  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Check Input Resolution block

Description

The Check Input Resolution block checks whether the input signal has a specified scalar or vector resolution. If the resolution is a scalar, the input signal must be a multiple of the resolution within a 10e-3 tolerance. If the resolution is a vector, the input signal must equal an element of the resolution vector. If the verification condition is true, the block does nothing. If not, the block halts the simulation, by default, and displays an error message.

Use the blocks in the Model Verification library to facilitate creation of self-validating models. For example, you can use model verification blocks to test that signals do not exceed specified limits during simulation. When you are satisfied that a model is correct, you can turn error checking off by disabling the verification blocks. You do not have to remove them from the model. If you need to modify a model, you can temporarily turn the verification blocks back on to ensure that your changes do not break the model.

Ports

Input

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Input signal that the block checks the resolution specified by the Resolution parameter.

Data Types: double

Output

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Output signal at each time step that is true (1) if the assertion succeeds, and false (0) if the assertion fails. If, in the Configuration Parameters, you select Implement logic signals as Boolean data, then the output data type is a Boolean. Otherwise the data type of the signal is a double.

Dependencies

To enable this output port, select the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

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Specify the resolution requirement for the input signal.

Command-Line Information

Parameter: resolution
Type: character vector
Values: '1' | real value
Default: '1'

Clearing this check box disables the block and causes the model to behave as if the block does not exist. You can set the Model Verification block enabling setting in the Configuration Parameters to enable or disable all model verification blocks in a model regardless of the setting of this option.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ' '

Select this check box to indicate that the block halts simulation when the check fails. Clear to indicate that the software displays a warning and continues the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Selecting this check box causes the block to output a Boolean signal that is true (1) at each time step if the assertion succeeds and false (0) if the assertion fails. The data type of the output signal is Boolean if you have selected the Implement logic signals as Boolean data check box on the Configuration Parameters dialog box. Otherwise the data type of the output signal is double.

Command-Line Information

Parameter: export
Type: character vector
Values: 'on' | 'off'
Default: 'off'

Block Characteristics

Data Types

double

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

no

Zero-Crossing Detection

no

Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Introduced before R2006a

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