High Throughput HDL Algorithms

You can increase the throughput of HDL designs by using frame-based processing. The ports of these blocks can use column vector input and output signals. Each element of the vector represents a sample in time. The generated HDL code implements the algorithm in parallel on each sample in the input vector. These implementations increase data throughput while using more hardware resources. Use vector input to achieve giga-sample-per-second (GSPS) throughput.

For more information on frame-based design, see Sample- and Frame-Based Concepts.

Blocks with HDL Support for Frame Input

Supported BlockParameters to Enable Frame InputLimitations
Discrete FIR Filter (Simulink)

  1. Connect a column vector to the input port. The input vector size can be up to 512 samples.

  2. Set Input processing to Columns as channels (frame based).

  3. Right-click the block, open HDL Code > HDL Block Properties, and set the Architecture to Frame Based.

For more information on HDL architectures and parameters, see the HDL Code Generation (Simulink) section of the block page.

Frame-based input is not supported with:

  • Optional block-level reset and enable control signals

  • Resettable and enabled subsystems

  • Complex input signals with complex coefficients. You can use either complex input signals and real coefficients, or complex coefficients and real input signals.

  • Multichannel input

  • Sharing and streaming optimizations

  • Filter structure set to anything other than Direct form.

FFT HDL Optimized and IFFT HDL OptimizedConnect a column vector to the dataIn port. The vector size must be a power of 2 between 1 and 64, that is not greater than the FFT length. Frame-based input is supported only when Architecture is set to Streaming Radix 2^2.
Channelizer HDL OptimizedConnect a column vector to the dataIn port. The vector size must be a power of 2 between 1 and 64, that is not greater than the FFT length.  
FIR Decimation HDL OptimizedConnect a column vector to the input data port. The vector size must be less than or equal to 64 samples.The decimation factor must be an integer multiple of the input vector size.
FIR Decimation

  1. Connect a column vector to the input port. The input vector size can be up to 512 samples.

  2. Set Input processing to Columns as channels (frame based).

  3. Set Rate options to Enforce single-rate processing.

  4. Right-click the block, open HDL Code > HDL Block Properties, and set the Architecture to Frame Based.

Frame-based input is not supported with:

  • Resettable and enabled subsystems

  • Complex input signals with complex coefficients. You can use either complex input signals and real coefficients, or complex coefficients and real input signals.

  • Sharing and streaming optimizations

NCO HDL OptimizedSet the Samples per frame parameter to the desired output vector size.  
CIC Decimation HDL OptimizedConnect a column vector to the input data port. The input vector size can be up to 64 samples.Frame-based input is supported only when Variable decimation factor is not selected.
Complex to Magnitude-Angle HDL OptimizedConnect a column vector to the input data port. The input vector size can be up to 64 samples. 
Delay

  1. Connect a column vector to the input port. The input vector size can be up to 512 samples.

  2. Set Input processing to Columns as channels (frame based).

 

Related Topics

DSP System Toolbox Documentation

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