Implement FFT for FPGA Using FFT HDL Optimized Block
This example shows how to use the FFT HDL Optimized block to implement a FFT for hardware.
The FFT and IFFT HDL Optimized blocks and system objects support simulation and HDL code generation for many applications. They provide two architectures optimized for different use cases:
Streaming Radix 2^2- For high throughput applications. Achieves gigasamples per second (GSPS) when you use vector input.Burst Radix 2- For low area applications. Uses only one complex butterfly.
This example includes two models that show how to use the streaming and burst architectures of the FFT HDL Optimized block, respectively.
Streaming Radix 2^2 Architecture
Modern ADCs are capable of sampling signals at sample rates up to several gigasamples per second. However, clock speeds for the fastest FPGA fall short of this sample rate. FPGAs typically run at hundreds of MHz. One way to perform GSPS processing on an FPGA is to process multiple samples at the same time at a much lower clock rate. Many modern FPGAs support the JESD204B standard interface that accepts scalar input at GHz clock rate and produces a vector of samples at a lower clock rate. Therefore modern signal processing requires vector processing.
The Streaming Radix 2^2 architecture is designed to support the high throughput use case. This example model uses an input vector size of 8, and calculates the FFT using the Streaming Radix 2^2 architecture. For timing diagram, supported features, and FPGA resource usage, see the FFT HDL Optimized block reference page.
modelname = 'FFTHDLOptimizedExample_Streaming';
open_system(modelname);
The InitFcn callback (Model Properties > Callbacks > InitFcn) sets parameters for the model. In this example, the parameters control the size of the FFT and the input data characteristics.
FFTLength = 512;
The input data is two sine waves, 200 KHz and 250 KHz, each sampled at 1*2e6 Hz. The input vector size is 8 samples.
FrameSize = 8; Fs = 1*2e6;
To demonstrate that data does not need to come continuously, this example applies valid input every other cycle.
ValidPattern = [1,0];
Open the Spectrum Viewer and run the example model.
open_system('FFTHDLOptimizedExample_Streaming/Spectrum Viewer/Power Spectrum viewer');
sim(modelname);
Burst Radix 2 (Minimum Resource) Architecture
Use the Burst Radix 2 architecture for applications with limited FPGA resources, especially when the FFT length is big. This architecture uses only one complex butterfly to calculate the FFT. The design accepts data while ready is asserted, and starts processing once the whole FFT frame is saved into the memory. While processing, the design cannot accept data, so ready is de-asserted. For timing diagram, supported features, and FPGA resource usage, see the FFT HDL Optimized block reference page.
modelname = 'FFTHDLOptimizedExample_Burst';
open_system(modelname);
The InitFcn callback (Model Properties > Callbacks > InitFcn) sets parameters for the model. In this example, the parameters control the size of the FFT and the input data characteristics.
FFTLength = 512;
The input data is two sine waves, 200 KHz and 250 KHz, each sampled at 1*2e6 Hz. Data is valid every cycle.
Fs = 1*2e6; ValidPattern = 1;
Open the Spectrum Viewer and run the example model.
open_system('FFTHDLOptimizedExample_Burst/Spectrum Viewer/Power Spectrum viewer');
sim(modelname);
Generate HDL Code and Test Bench
An HDL Coder™ license is required to generate HDL for this example.
Choose one of the models to generate HDL code and test bench:
systemname = 'FFTHDLOptimizedExample_Burst/FFT HDL Optimized Burst';
or
systemname = 'FFTHDLOptimizedExample_Streaming/FFT HDL Optimized Streaming';
Use this command to generate HDL code for either FFT mode. The generated can be used for any FPGA or ASIC target.
makehdl(systemname);
Use this command to generate a test bench that compares the results of an HDL simulation against the Simulink simulation behavior.
makehdltb(systemname);