Configure Board-Specific Setup Information

Note

For setting up the boards, you do not need an Ethernet cable or an SD card.

Xilinx Zynq-7000 ZC706 Evaluation Board

This figure shows how to set up the Xilinx® Zynq®-7000 ZC706 evaluation board. To set up the board:

  1. Configure SW4 shown in the image below, and to use Digilent USB-TO-JTAG interface using the following configuration table:

    Configuration SourceSW4 switch 1SW4 switch 2
    None00
    Cable Connector J310
    Digilent USB-TO-JTAG Interface 01
    JTAG (flying lead)Header J6211

  2. Plug the power cord and then connect the host computer to the FPGA board by using a JTAG cable as shown in the image below:

  3. To use Ethernet, see Create Target Object That Has an Ethernet Interface and Set IP Address.

  4. To learn more about the board configuration, see Xilinx ZC706 Evaluation Board User Guide.

After you have set up the connection to the board, to run the workflow:

  1. Create a workflow object by using the bitstream name that is provided for the board as mentioned in Use Deep Learning Bitstreams (Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices) .

  2. To learn more about the workflow, see Prototype Deep Learning Networks on FPGA and SoCs Workflow.

Intel Arria 10 SoC development kit

This figure shows how to set up the Intel® Arria® 10 SoC development kit. To set up the board:

  1. Plug the power cord and then connect the host computer to the FPGA board by using a JTAG cable.

  2. Specify the SW3 switch settings:

    Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8
    OffOnOnOnOnOffOffOff

  3. Connect two DDR4 plugin boards to the memory plugin slot.

  4. To use Ethernet, see Create Target Object That Has an Ethernet Interface and Set IP Address.

This figure shows the configuration settings for the Intel Arria 10 SoC development kit.

To learn more about the board configuration, see Arria 10 SoC Development Kit User Guide.

After you have set up the connection to the board, to run the workflow:

  1. Create a workflow object by using the bitstream name that is provided for the board as mentioned in Use Deep Learning Bitstreams (Deep Learning HDL Toolbox Support Package for Intel FPGA and SoC Devices) .

  2. To learn more about the workflow, see Prototype Deep Learning Networks on FPGA and SoCs Workflow.

Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA Development Board

1. Set up the Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as shown in the figure below:

To setup the board:

  1. Plug in the power cord. If using JTAG connect the FPGA board to the host computer using a JTAG cable. If using Ethernet connect the FPGA board to the host computer using an Ethernet cable.

  2. Configure SW6 switch which is shown in the image below:

    Use the configuration table below to configure the switch settings:

    Boot ModeMode Pins [3:0]SW6 Switch Position [3:0]
    JTAG0, 0, 0, 0on, on, on, on
    QSPI320, 0, 1, 0 on, on, off, on
    SD1, 1, 1, 0off, off, off, on

    The SW6 default position is QSPI32. For the SW6 DIP switch moving the switch towards the ON label is a 0.

  3. To use Ethernet, see Create Target Object That Has an Ethernet Interface and Set IP Address.

  4. To learn more about the ZCU102 hardware setup, please refer to Xilinx documentation

After you have set up the connection to the board, to run the workflow:

  1. Create a workflow object by using the bitstream name that is provided for the board as mentioned in Use Deep Learning Bitstreams (Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices) .

  2. To learn more about the workflow, see Prototype Deep Learning Networks on FPGA and SoCs Workflow.

Deep Learning HDL Toolbox Documentation

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