Area and timing optimizations that you specify can result in upsampled rates in your design.
For example, when you use the resource sharing optimization, the code generator
overclocks the shared resources by an overclocking factor (OCF). The OCF depends on
the number of shareable resources, N, and the
SharingFactor, SF, that you specify. If
your clock rate is high, overclocking can cause your design clock rate to exceed the
maximum clock rate of your target hardware. To constrain overclocking, use the
Oversampling factor in conjunction with clock-rate
pipelining to constrain the overclocking of your design.
Area and speed optimizations, and certain block implementations that you specify result in overclocking the resources in your design. For example, the following optimizations and implementations can result in upsampled rates in your design:
RAM mapping
Streaming
Resource sharing
Loop streaming
Specific block implementations, such as cascade architectures, Newton-Raphson architectures, and some filter implementations
When using area and speed optimizations, you can specify constraints on overclocking using the
oversampling parameter. If you want a single-rate design,
you can use these parameters to prevent overclocking, or limit overclocking within a
range.
Suppose that you have a design that does not currently fit in the target hardware, but is
already running at the target device maximum clock frequency, and you know that the
inputs to your design can change at most every N cycles. You can
enable area optimizations, such as resource sharing, and specify a single-rate
implementation using the Oversampling factor. You can specify
the Oversampling factor in the HDL Code Generation > Global Settings pane of the Configuration Parameters dialog box.
By default, the clock-rate pipelining optimization is enabled, and it works in
conjunction with the Oversampling factor to make the DUT sample
time slower than the actual clock rate. You can design your model at the base sample
time and then set the Oversampling factor to
N. This setting gives HDL Coder™ a latency budget of N cycles to perform the computation. In this
situation, HDL Coder can reuse the shared resource at the original clock rate over N
cycles, instead of implementing the sharing optimization by overclocking the shared
resource.
When you constrain overclocking by specifying an Oversampling factor
greater than 1, ClockInputs must be set to
Single.