Locate Numeric Differences After Speed Optimization
This example first selects a speed-optimized Sum block implementation for simple model that computes a vector sum. It then examines a generated model and locates the numeric changes introduced by the optimization.
The model, simplevectorsum, consists of a Subsystem,
vsum, driven by a vector input of width 10, with a scalar output.
The following figure shows the root level of the model.
The device under test is the vsum subsystem, shown in the following
figure. The subsystem contains a Sum block, configured for vector summation.
The model is configured to use the Tree implementation when
generating HDL code for the Sum block within the vsum subsystem. This
implementation, optimized for minimal latency, generates a tree-shaped structure of
adders for the Sum block.
To select a nondefault implementation for an individual block:
Right-click the block and select HDL Code > HDL Block Properties .
In the HDL Properties dialog box, select the desired implementation from the Architecture menu.
Click Apply and close the dialog box.
After code generation, you can view the validation model,
gm_simplevectorsum_tree_vnl.
The vsum subsystem has been highlighted in cyan. This highlighting
indicates that the subsystem differs in some respect from the vsum
subsystem of the original model.
The following figure shows the vsum subsystem in the generated
model. Observe that the Sum block is now implemented as a subsystem, which also appears
highlighted.
The following figure shows the internal structure of the Sum subsystem.
The generated model implements the vector sum as a tree of adders (Sum blocks). The vector input signal is demultiplexed and connected, as five pairs of operands, to the five leftmost adders. The widths of the adder outputs increase from left to right, as required to avoid overflow in computing intermediate results.