HDL Coder™ native floating-point can generate target-independent HDL code from your floating-point design. You can synthesize your floating-point design on any generic FPGA or ASIC. Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.
HDL Coder supports several Simulink® blocks including math and trigonometric blocks with native floating-point technology.
In the HDL Floating Point Operations library, HDL Coder supports all blocks that have
single and double data types in the Native
Floating Point mode.
Certain blocks such as Discrete-Time Integrator and Discrete PID
Controller are supported in Native Floating Point mode only
when they use zero latency strategy. These blocks contain inherent feedback loops and
using a nonvalue for the latency strategy can result in the code generator being unable to
allocate delays. For more information, see Allocate Sufficient Delays for Floating-Point Operations.
In the Math Operations library, these blocks are
supported:
| Block Name | Supported with single data types | Supported with double data types |
|---|---|---|
| Abs | Yes | Yes |
| Add | Yes | Yes |
| Assignment | Yes | Yes |
| Bias | Yes | Yes |
| Complex to Real-Imag | Yes | Yes |
| Divide | Yes | Yes |
| Dot Product | Yes | Yes |
| Gain | Yes | Yes |
| Math Function | Yes | No |
| MinMax | Yes | Yes |
| Product | Yes | Yes |
| Product of Elements | Yes | Yes |
| Real-Imag to Complex | Yes | Yes |
| Reciprocal Sqrt | Yes | Yes |
| Reshape | Yes | Yes |
| Sqrt | Yes | Yes |
| Subtract | Yes | Yes |
| Sum | Yes | Yes |
| Sum of Elements | Yes | Yes |
| Trigonometric Function | Yes | No |
| Unary Minus | Yes | Yes |
| Vector Concatenate | Yes | Yes |
The table shows the list of supported blocks in other HDL Coder block libraries.
| Block Library | Supported blocks with single and double data types |
|---|---|
Discrete | The supported blocks include Zero Order Hold and the set of delay blocks including Integer Delay and Tapped Delay. |
HDL Operations | All blocks are supported. |
HDL RAMs | All blocks are supported. |
HDL Subsystems | All blocks are supported. |
Logic and Bit Operations | All blocks are supported. |
Lookup Tables | Table data of Direct Lookup Table (n-D) and n-D Lookup Table blocks are supported with floating-point data types. The inputs must not use floating-point types. |
Model Verification | All blocks are supported. |
Model-Wide Utilities | All blocks are supported. |
Ports & Subsystems | Enable, reset, input, and output ports, model references, and subsystem blocks are supported. |
Signal Attributes | All blocks are supported. |
Signal Routing | All blocks are supported. |
Sources | The supported blocks include Inport, Constant, and Ground blocks. |
Sinks | All blocks are supported. |
User-Defined Functions | MATLAB Function blocks are supported. |
In native floating-point mode, the code generator does not support these blocks or block architectures:
Biquad Filter.
Switch block with input to the control port as a floating-point type.
Sum of Elements with complex input types.
MATLAB System blocks.
Dot Product in complex mode with Architecture as
Tree or Linear.
Discrete FIR Filter with Architecture other than
Fully Parallel.
Dead Zone and Dead Zone Dynamic.
Polar to Cartesian.
For the Data Type Conversion block:
Stored Integer (SI) mode for Input and
output to have equal setting is not supported.
The Saturate on integer overflow check box must be left cleared.