Fixed-Point Bitwise Functions

The following table summarizes bitwise functions in MATLAB^® and Fixed-Point Designer™ that are supported for HDL code generation. The following conventions are used in the table:

a,b: Denote fixed-point integer operands.
idx: Denotes an index to a bit within an operand. Indexes can be scalar or vector, depending on the function.
MATLAB code uses 1-based indexing conventions. In generated HDL code, such indexes are converted to zero-based indexing conventions.
lidx, ridx: denote indexes to the left and right boundaries delimiting bit fields. Indexes can be scalar or vector, depending on the function.
val: Denotes a Boolean value.

Note

Indexes, operands, and values passed as arguments bitwise functions can be scalar or vector, depending on the function. For information on the individual functions, see Bitwise Operations (Fixed-Point Designer).

MATLAB Syntax	Description	See Also
`bitand(a, b)`	Bitwise AND	`bitand`
`bitandreduce(a, lidx, ridx)`	Bitwise AND of a field of consecutive bits within `a`. The field is delimited by `lidx` , `ridx`. Output data type: `ufix1` For VHDL^®, generates the bitwise AND operator operating on a set of individual slices For Verilog^®, generates the reduce operator: &a[lidx:ridx]	`bitandreduce`
`bitcmp(a)`	Bitwise complement	`bitcmp`
`bitconcat(a, b)` `bitconcat([a_vector])` `bitconcat(a, b,c,d,...)`	Concatenate fixed-point operands. Operands can be of different signs. Output data type: `ufixN`, where `N` is the sum of the word lengths of `a` and `b`. For VHDL, generates the concatenation operator: `(a & b)` For Verilog, generates the concatenation operator: `{a , b}`	`bitconcat`
`bitget(a,idx)`	Access a bit at position `idx`. For VHDL, generates the slice operator: `a(idx)` For Verilog, generates the slice operator: `a[idx]`	`bitget`
`bitor(a, b)`	Bitwise OR	`bitor`
`bitorreduce(a, lidx, ridx)`	Bitwise OR of a field of consecutive bits within `a`. The field is delimited by `lidx` and `ridx`. Output data type: `ufix1` For VHDL, generates the bitwise OR operator operating on a set of individual slices. For Verilog, generates the reduce operator: \|a[lidx:ridx]	`bitorreduce`
`bitset(a, idx, val)`	Set or clear bit(s) at position `idx`. If `val = 0`, clears the indicated bit(s). Otherwise, sets the indicated bits.	`bitset`
`bitreplicate(a, n)`	Concatenate bits of `fi` object `a` `n` times	`bitreplicate`
`bitrol(a, idx)`	Rotate left. `idx` must be a positive integer. The value of `idx` can be greater than the word length of `a`. `idx` is normalized to `mod(idx, wlen)`. `wlen` is the word length of `a`. For VHDL, generates the `rol` operator. For Verilog, generates the following expression (where `wl` is the word length of `a`: a << idx \|\| a >> wl - idx	`bitrol`
`bitror(a, idx)`	Rotate right. `idx` must be a positive integer. The value of `idx` can be greater than the word length of `a`. `idx` is normalized to `mod(idx, wlen)` . `wlen` is the word length of `a`. For VHDL, generates the `ror` operator. For Verilog, generates the following expression (where `wl` is the word length of `a`: a >> idx \|\| a << wl - idx	`bitror`
`bitset(a, idx, val)`	Set or clear bit(s) at position `idx`. If `val = 0`, clears the indicated bit(s). Otherwise, sets the indicated bits.	`bitset`
`bitshift(a, idx)`	Note: For efficient HDL code generation, use `bitsll`, `bitsrl`, or `bitsra` instead of `bitshift`. Shift left or right, based on the positive or negative integer value of‘`idx`. `idx` must be an integer. For positive values of `idx`, shift left `idx` bits. For negative values of `idx`, shift right `idx` bits. If `idx` is a variable, generated code contains logic for both left shift and right shift. Result values saturate if the `overflowMode` of `a` is set to `saturate`.	`bitshift`
`bitsliceget(a, lidx, ridx)`	Access consecutive set of bits from `lidx` to `ridx`. Output data type: `ufixN`, where `N = lidx-ridix+1`.	`bitsliceget`
`bitsll(a, idx)`	Shift left logical. `idx` must be a scalar within the range 0 <= idx < wl `wl` is the word length of `a`. Overflow and rounding modes of input operand `a` are ignored. Generates `sll` operator in VHDL. Generates `<<` operator in Verilog.	`bitsll`
`bitsra(a, idx)`	Shift right arithmetic. `idx` must be a scalar within the range 0 <= idx < wl `wl` is the word length of `a`, Overflow and rounding modes of input operand `a` are ignored. Generates `sra` operator in VHDL. Generates `>>>` operator in Verilog.	`bitsra`
`bitsrl(a, idx)`	Shift right logical. `idx` must be a scalar within the range 0 <= idx < wl `wl` is the word length of `a`. Overflow and rounding modes of input operand `a` are ignored. Generates `srl` operator in VHDL. Generates `>>` operator in Verilog.	`bitsrl`
`bitxor(a, b)`	Bitwise XOR	`bitxor`
`bitxorreduce(a, lidx, ridx)`	Bitwise XOR reduction. Bitwise XOR of a field of consecutive bits within `a`. The field is delimited by `lidx` and `ridx`. Output data type: `ufix1` For VHDL, generates a set of individual slices. For Verilog, generates the reduce operator: ^a[lidx:ridx]	`bitxorreduce`
`getlsb(a)`	Return value of LSB.	`getlsb`
`getmsb(a)`	Return value of MSB.	`getmsb`

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Fixed-Point Bitwise Functions

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