Introduction

The HIL implementation of a Simscape model on Speedgoat FPGA I/O is a three-step process.

Simulink™ Implementation of the Simscape Model

This example shows a step-by-step process to generate a Simulink model from the Simscape model of a Half Wave Rectifier. The following steps are to be performed to configure the Simscape model:

1. Open The Simscape model. In the MATLAB® command prompt, enter:

   ModelName = 'sschdlexHalfWaveRectifierExample';
   load_system(ModelName)
   open_system(ModelName)
   set_param(ModelName, 'SimulationCommand', 'update');

The Simscape model of a Half Wave Rectifier consists of a Linear block (resistor) and a Switched Linear block (diode). It has Simulink-PS converter blocks at the input and PS-Simulink Converter blocks at the output ports. To verify that the solver settings are configured correctly, open the Solver Configuration block, and then select Use local solver and Backward Euler as the Solver type in the Solver Configuration Block.

The following figure shows simulation results of the Simscape model. Here, the input is a sine wave and local solver sample time is 0.001.

2. Configure the Half Wave Rectifier Model for HDL compatibility using the following command:

   hdlsetup(ModelName)

### The configuration parameter values use the recommended settings for HDL code generation and does not need any modification as a part of hdlsetup. Please refer to <a href="matlab:helpview(fullfile(docroot, 'hdlcoder', 'helptargets.map'), 'msg_hdlsetup_function')">hdlsetup</a> document for best practices on model settings.

Now the Simscape model is ready for generating the HDL implementation model from which you can generate bitstream. To generate the HDL implementation model, open the Simscape HDL Workflow Advisor by running the following command:

   sschdladvisor(ModelName)

### Running Simscape HDL Workflow Advisor for <a href="matlab:(sschdlexHalfWaveRectifierExample)">sschdlexHalfWaveRectifierExample</a>
Updating Model Advisor cache...
Model Advisor cache updated. For new customizations, to update the cache, use the Advisor.Manager.refresh_customizations method.

This updates the model advisor cache and opens the Simscape HDL Workflow Advisor. The Advisor contains the following folders:

Upon passing, this task displays the number of states, inputs, outputs, and modes.

To learn more about the tasks, see Simscape HDL Workflow Advisor Tasks.

To open the generated model, click the link in the Generate Implementation Model task.

To compare the outputs of the implementation model and the original Simscape model, open up the Scope, and change the Layout to 3x1

The output of this model is similar to that of the Simscape model which indicates that no accuracy loss occurred during the conversion. For a systematic verification of this conversion see Validate HDL Implementation Model to Simscape Algorithm.

To learn more about Simscape HDL Workflow Advisor, see: Generate HDL Code for Simscape Models.

Generate Bitstream for Speedgoat Platform

This step explains the tasks that are performed to generate the FPGA bitstream from the Half Wave Rectifier model. The bitstream is then downloaded onto the Speedgoat IO333-325K FPGA module by using the HDL Workflow Advisor. The Speedgoat IO333 FPGA module uses Xilinx® Vivado® and IP Core Generation Infrastructure. Therefore, prior to running the Workflow Advisor, make sure that you have specified the path to the installed Xilinx Vivado executable.

To deploy any model onto Speedgoat target, at first you need to setup and configure the synthesis tool. In this example we will use Speedgoat FPGA IO333-325K that uses Xilinx Vivado. Therefore, install Xilinx Vivado Design Suite v2018.2. Then run the following command in MATLAB command window to set the tool path to the installed Xilinx executable.

  hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2018.2\bin\vivado.bat')

Open HDL Workflow Advisor using the following command:

  hdladvisor('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/HDL Subsystem')

HDL workflow advisor provides an interface where user can set target parameters, prepare the model for HDL code generation and finally generate the corresponding HDL code or bitstream. Following tasks need to be completed to generate and build FPGA bitstream.

1. Set Target :

a. *Set Target Device and Synthesis Tool* subtask, select:

b. Set Target Reference Design task, select x4 as the parameter value for PCIe lanes.

c. Set Target Interface task, map the Input and Output single data type ports to PCIe Interface.

d. Set Target Frequency task, set the target frequency as 100 MHz. It is important to select a target frequency withing the range in order to avoid error in bitstream generation. In this example we select the target frequency as 100 MHz.

2. Prepare Model For HDL Code Generation : This task makes the model ready for bitstream generation by ensuring correct parameters have been selected.

There may be a warning in the Check Block Compatibility subtask for Loop Optimization. Selecting Ignore warnings checkbox will continue running the task.

3. Right-click the "Download to Target > Generate Simulink Real-Time task" task and select "Run to Selected Task" to generate the HDL IP core, FPGA bitstream, and download the bitstream onto the Speedgoat IO333 target

For detailed understanding on how to generate bitstream please see Deploy Simscape™ Plant Models to Speedgoat FPGA I/O Modules.

Upon completing this task a new Simulink Real-Time Interface model is generated which is similar to the following model and named as gm_gmStateSpaceHDL_sschdlexHalfWaveRectifierEx_slrt :

This model will be downloaded to the Speedgoat target. After the completion of the last step, the workflow can be saved for future use. In order to save the workflow, select File > Export to Script . This is will export a .m file named hdlworkflow.m.

This can be imported by selecting File > Import from Script. This will open the Import Workflow Configuration dialog box from where user can select the hdlworkflow.m file. The HDL Workflow Advisor updates the tasks according to the imported script. See Run HDL Workflow with a Script.

Deploy Bitstream to Speedgoat IO333-325k Target

This is the last step of this tutorial which includes configuration of Simulink Real-Time, build and download the generated Simulink Real-Time Interface model from the previous step by creating a real-time application and run the application in Speedgoat target.

1. Setup and Configure Simulink Real-Time : The bitstream is downloaded through the Simulink Real-Time explorer. Therefore, it is important to setup and configure Simulink Real-Time explorer. At first, connect the development computer to the target using a cross-over network cable. In this case, Speedgoat Target IP address is 10.10.10.15. Therefore, the IP address of the communication link between the development computer and target computer should be of the same network (i.e; 10.10.10.12).

Now perform the following steps to configure Simulink Real-Time explorer correctly:

2. Create Real-Time Application : This task is required to finally download the model onto the Speedgoat target. Following steps need to be followed:

3. Build and Run Real-Time Application :

tg.viewTargetScreen

The output waveforms in the Target Scope should look like the following:

Since the simulation results of the downloaded model exactly match with the original Simscape model, the accuracy loss is zero or minimal.