%% Profile Network for Performance Improvement
% This example shows how to improve the performance of the deployed deep learning network, by identifying bottle neck layers from the profiler results.
%% Prerequisites
% Xilinx™ ZCU102 SoC development kit.
% Deep Learning HDL Toolbox™ Support Package for Xilinx™ FPGA and SoC
% Deep Learning Toolbox™
% Deep Learning HDL Toolbox™
%%
%
%% Load the Pretrained SeriesNetwork
% To load the pretrained digits series network, enter:

snet = getDigitsNetwork();

% To view the layers of the pretrained series network, enter:
snet.Layers

%
%% Create Target Object
% Create a target object that has a custom name for your target device and an interface to connect your target device to the host computer. Interface options are JTAG and Ethernet. For Ethernet interface, enter:

hTarget = dlhdl.Target('Xilinx','Interface','Ethernet');

% To use the JTAG interface, install Xilinx™ Vivado™ Design Suite 2019.2. Set up the path to your installed Xilinx Vivado executable if it is not already set up. For example, to set the toolpath, enter:

% hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.2\bin\vivado.bat');

% For JTAG interface, enter:

% hTarget = dlhdl.Target('Xilinx','Interface','JTAG');

%
%% Create WorkFlow Object
% Create an object of the dlhdl.Workflow class. When you create the object, specify the network and the bitstream name. Specify the saved pretrained digits neural network, snet, as the network. Make sure that the bitstream name matches the data type and the FPGA board that you are targeting. In this example the target FPGA board is the Xilinx ZCU102 SOC board. The bitstream uses a single data type.

hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'zcu102_single', 'Target', hTarget);
%
% If running on Xilinx ZC706 board, instead of the above command, 
% uncomment the command below.
%
% hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'zc706_single','Target',hTarget);

%
%% Compile MNIST Series Network
% To compile the MNIST series network, run the compile function of the dlhdl.Workflow object.

dn = hW.compile;

%
%% Program Bitstream onto FPGA and Download Network Weights
% To deploy the network on the Xilinx ZCU102 SoC hardware, run the deploy function of the dlhdl.Workflow object. This function uses the output of the compile function to program the FPGA board by using the programming file. It also downloads the network weights and biases.

hW.deploy;

%
%% Load Example Image
% Load the example image.

inputImg = imread('five_28x28.pgm');

%
%% Run the Prediction
% Execute the predict function of the dlhdl.Workflow object that has profile option set to 'on' to display the latency and throughput results.

[~, speed] = hW.predict(single(inputImg),'Profile','on');

%
%% Identify and Display the Bottle Neck Layer
% Remove the NumFrames, Total latency, and Frames/s from the profiler's results table. This includes removing the module level and network level profiler results. Retain only the network layer profiler results. Once the bottle neck layer has been identified display the bottle neck layer index, running time, and information.

speed('Network',:) = [];
speed('____conv_module',:) = [];
speed('____fc_module',:)  = [];
speed = removevars(speed, {'NumFrames','Total Latency(cycles)','Frame/s'});

% then sort the profiler's results in descending ordering
speed = sortrows(speed,'Latency(cycles)','descend');

% the first row in the profile table is the bottleneck layer. Thus the
% following 
layerSpeed = speed(1,:);
layerName = strip(layerSpeed.Properties.RowNames{1},'_');
for idx = 1:length(snet.Layers)
    currLayer = snet.Layers(idx);
    if strcmp(currLayer.Name, layerName)
        bottleNeckLayer = currLayer;
        break;
    end
end

% disply the bottle neck layer index 
dnnfpga.disp(['Bottleneck layer index is ', num2str(idx), '.']);

% disply the bottle neck layer running time percentage  
percent = layerSpeed.("Latency(cycles)")/sum(speed.("Latency(cycles)")) * 100;
dispStr = sprintf('It accounts for about %0.2f percent of the total running time.', percent);
dnnfpga.disp(dispStr);

% disply the bottle neck layer information  
dnnfpga.disp('Bottleneck layer information: ');
disp(currLayer);

% Copyright 2020 The MathWorks, Inc.