%% Logo Recognition Network
% This example shows how to create, compile, and deploy a dlhdl.Workflow object that has Logo Recognition Network as the network object using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.
%% The Logo Recognition Network
% Logos assist users in brand identification and recognition. Many companies incorporate their logos in advertising, documentation materials, and promotions. The logo recognition network (logonet) was developed in MATLAB® and can recognize 32 logos under various lighting conditions and camera motions. Because this network focuses only on recognition, you can use it in applications where localization is not required.
%% Prerequisites
% Xilinx ZCU102 SoC development kit
% Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC
% Deep Learning Toolbox™
% Deep Learning HDL Toolbox™
%%
%
%% Load the Pretrained Series Network
% To load the pretrained series network logonet, enter:

snet = getLogoNetwork();

%
% To view the layers of the pretrained series network, enter:

analyzeNetwork(snet)

%
%
%
%% Create Target Object
% Create a target object that has a custom name for your target device and an interface to connect your target device to the host computer. Interface options are JTAG and Ethernet. To use JTAG, install Xilinx™ Vivado™ Design Suite 2019.2. To set the Xilinx Vivado toolpath, enter:

% hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.2\bin\vivado.bat');

% To create the target object, enter:

hTarget = dlhdl.Target('Xilinx','Interface','Ethernet');

%
%% Create WorkFlow Object
% Create an object of the dlhdl.Workflow class. When you create the object, specify the network and the bitstream name. Specify the saved pretrained logonet neural network, snet, as the network. Make sure that the bitstream name matches the data type and the FPGA board that you are targeting. In this example the target FPGA board is the Xilinx ZCU102 SOC board. The bitstream uses a single data type.

hW = dlhdl.Workflow('network', snet, 'Bitstream', 'zcu102_single','Target',hTarget);
% If running on Xilinx ZC706 board, instead of the above command, 
% uncomment the command below.
%
% hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'zc706_single','Target',hTarget);

%
%% Compile the Logo Recognition Network
% To compile the logo recognition network, run the compile function of the dlhdl.Workflow object.

dn = hW.compile

%
%% Program Bitstream onto FPGA and Download Network Weights
% To deploy the network on the Xilinx ZCU102 SoC hardware, run the deploy function of the dlhdl.Workflow object. This function uses the output of the compile function to program the FPGA board by using the programming file. It also downloads the network weights and biases. The deploy function starts programming the FPGA device, displays progress messages, and the time it takes to deploy the network.

 hW.deploy

%
%% Load the Example Image
% Load the example image.

image = imread('heineken.png');
inputImg = imresize(image, [227, 227]);
imshow(inputImg);

%
%% Run the Prediction
% Execute the predict function on the dlhdl.Workflow object and display the result:

[prediction, speed] = hW.predict(single(inputImg),'Profile','on');
[val, idx] = max(prediction);
snet.Layers(end).ClassNames{idx}

% Copyright 2020 The MathWorks, Inc.
%