Index of /nchou/s/matlab-2020b/amd64_ubu18/amd64_rhel7/toolbox/shared/hdlshared

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[DIR]+hdlconnectivity/2021-01-21 13:17 -  
[DIR]+hdlshared/2021-01-21 13:17 -  
[DIR]@fdhdlcoderui/2021-01-21 13:17 -  
[DIR]@hdl/2021-01-21 13:17 -  
[DIR]@hdlcoderprops/2021-01-21 13:17 -  
[DIR]@hdlfilter/2021-01-21 13:17 -  
[DIR]@hdlshared/2021-01-21 13:17 -  
[DIR]@multicycleconstraints/2021-01-21 13:17 -  
[DIR]@propset/2021-01-21 13:17 -  
[DIR]@reportdlg/2021-01-21 13:17 -  
[   ]Contents.m2011-05-10 20:38 162  
[TXT]PersistentHDLPropSet.p2020-07-29 09:43 163  
[TXT]PersistentHDLResource.p2020-07-29 09:43 163  
[TXT]WebBrowserHandleCollector.p2020-07-29 09:43 379  
[TXT]attachhdlcconfig.p2020-07-29 09:43 478  
[TXT]checkSDRProductRequirements.p2020-07-29 09:43 189  
[TXT]checksymmetry.p2020-07-29 09:43 232  
[TXT]conv2hdlsharedtypes.p2020-07-29 09:43 204  
[TXT]detachhdlcconfig.p2020-07-29 09:43 394  
[TXT]dumphdlentitysignals.p2020-07-29 09:43 611  
[TXT]getHDLWAPluginManager.p2020-07-29 09:43 263  
[TXT]gethdlcc.p2020-07-29 09:43 181  
[TXT]gethdlcconfigset.p2020-07-29 09:43 345  
[TXT]getpirsignaltype.p2020-07-29 09:43 264  
[TXT]getslsignaltype.p2020-07-29 09:43 123  
[TXT]getslsignaltypefromval.p2020-07-29 09:43 130  
[TXT]hasQuantizationError.p2020-07-29 09:43 576  
[TXT]hdlCellArray2Str.p2020-07-29 09:43 286  
[TXT]hdlComponent.p2020-07-29 09:43 1.2K 
[TXT]hdlGetCodegendir.p2020-07-29 09:43 283  
[TXT]hdlUniquifyTypeDefinitions.p2020-07-29 09:43 415  
[TXT]hdladd.p2020-07-29 09:43 753  
[TXT]hdladdclockenablesignal.p2020-07-29 09:43 162  
[TXT]hdladdclocksignal.p2020-07-29 09:43 215  
[TXT]hdladdinportsignal.p2020-07-29 09:43 254  
[TXT]hdladdoutportsignal.p2020-07-29 09:43 257  
[TXT]hdladdresetsignal.p2020-07-29 09:43 213  
[TXT]hdladdsub.p2020-07-29 09:43 408  
[TXT]hdladdtoentitylist.p2020-07-29 09:43 417  
[TXT]hdlassignforoutput.p2020-07-29 09:43 330  
[TXT]hdlbitop.p2020-07-29 09:43 1.4K 
[TXT]hdlblockdatatype.p2020-07-29 09:43 217  
[TXT]hdlcascadedecompose.p2020-07-29 09:43 1.0K 
[TXT]hdlclockenablesignals.p2020-07-29 09:43 166  
[TXT]hdlclocksignals.p2020-07-29 09:43 161  
[TXT]hdlcodeconcat.p2020-07-29 09:43 176  
[TXT]hdlcodegenmode.p2020-07-29 09:43 253  
[TXT]hdlcodegenmsgs.p2020-07-29 09:43 880  
[TXT]hdlcodeinit.p2020-07-29 09:43 267  
[TXT]hdlcoeffmultiply.p2020-07-29 09:43 2.5K 
[TXT]hdlcompareval.p2020-07-29 09:43 1.5K 
[TXT]hdlconstantvalue.p2020-07-29 09:43 242  
[TXT]hdlcounter.p2020-07-29 09:43 521  
[TXT]hdldatatypeassignment.p2020-07-29 09:43 2.3K 
[TXT]hdldefarchheader.p2020-07-29 09:43 230  
[TXT]hdldefaultparameters.p2020-07-29 09:43 207  
[TXT]hdldeserializer.p2020-07-29 09:43 461  
[TXT]hdldisp.p2020-07-29 09:43 247  
[TXT]hdlentityfilenames.p2020-07-29 09:43 419  
[TXT]hdlentitynameexists.p2020-07-29 09:43 236  
[TXT]hdlentitynames.p2020-07-29 09:43 278  
[TXT]hdlentityportnames.p2020-07-29 09:43 168  
[TXT]hdlentityports.p2020-07-29 09:43 1.1K 
[TXT]hdlentitysignalsinit.p2020-07-29 09:43 190  
[TXT]hdlentitytop.p2020-07-29 09:43 204  
[TXT]hdlentitytopfilename.p2020-07-29 09:43 286  
[TXT]hdleqop.p2020-07-29 09:43 263  
[TXT]hdlexpandvectorsignal.p2020-07-29 09:43 1.0K 
[TXT]hdlfilteradd.p2020-07-29 09:43 412  
[TXT]hdlfilterlatency.p2020-07-29 09:43 617  
[TXT]hdlfiltermultiply.p2020-07-29 09:43 156  
[TXT]hdlfiltermultiplycsd.p2020-07-29 09:43 158  
[TXT]hdlfiltermultiplyfactoredcsd.p2020-07-29 09:43 162  
[TXT]hdlfiltersub.p2020-07-29 09:43 145  
[TXT]hdlfilterunaryminus.p2020-07-29 09:43 179  
[TXT]hdlfinalassignment.p2020-07-29 09:43 877  
[TXT]hdlfirinterpdamac.p2020-07-29 09:43 3.0K 
[TXT]hdlformatcomment.p2020-07-29 09:43 290  
[TXT]hdlgetallfromsltype.p2020-07-29 09:43 477  
[TXT]hdlgetblocklibpath.p2020-07-29 09:43 1.0K 
[TXT]hdlgetclockbundle.p2020-07-29 09:43 328  
[TXT]hdlgetcurrentclock.p2020-07-29 09:43 174  
[TXT]hdlgetcurrentclockenable.p2020-07-29 09:43 181  
[TXT]hdlgetcurrentreset.p2020-07-29 09:43 173  
[TXT]hdlgetdeviceinfo.p2020-07-29 09:43 172  
[TXT]hdlgetedascript.p2020-07-29 09:43 1.7K 
[TXT]hdlgetfilelink.p2020-07-29 09:43 275  
[TXT]hdlgetlintscript.p2020-07-29 09:43 1.5K 
[TXT]hdlgetmatlabsystemmap.p2020-07-29 09:43 277  
[TXT]hdlgetparameter.p2020-07-29 09:43 247  
[TXT]hdlgetpathtoquartus.p2020-07-29 09:43 416  
[TXT]hdlgetporttypesfromsizes.p2020-07-29 09:43 382  
[TXT]hdlgetsignaltable.p2020-07-29 09:43 189  
[TXT]hdlgetsizesfromtype.p2020-07-29 09:43 118  
[TXT]hdlgetsltypefromsizes.p2020-07-29 09:43 239  
[TXT]hdlgettypesfromsizes.p2020-07-29 09:43 392  
[TXT]hdlhandles.p2020-07-29 09:43 126  
[TXT]hdlinportsignals.p2020-07-29 09:43 203  
[TXT]hdlintdelay.p2020-07-29 09:43 668  
[TXT]hdlisclockenablesignal.p2020-07-29 09:43 212  
[TXT]hdlisclocksignal.p2020-07-29 09:43 208  
[TXT]hdlisinoutportsignal.p2020-07-29 09:43 179  
[TXT]hdlisinportsignal.p2020-07-29 09:43 153  
[TXT]hdlisoutportsignal.p2020-07-29 09:43 153  
[TXT]hdlispowerof2.p2020-07-29 09:43 303  
[TXT]hdlisresetsignal.p2020-07-29 09:43 208  
[TXT]hdlissignalscalar.p2020-07-29 09:43 111  
[TXT]hdlissignaltype.p2020-07-29 09:43 500  
[TXT]hdlissignalvector.p2020-07-29 09:43 176  
[TXT]hdllastinputsignal.p2020-07-29 09:43 216  
[TXT]hdllastoutputsignal.p2020-07-29 09:43 260  
[TXT]hdllastsignal.p2020-07-29 09:43 204  
[TXT]hdllegalizefieldname.p2020-07-29 09:43 228  
[TXT]hdllegalname.p2020-07-29 09:43 283  
[TXT]hdllegalnamersvd.p2020-07-29 09:43 228  
[TXT]hdllog.p2020-07-29 09:43 393  
[TXT]hdllogop.p2020-07-29 09:43 1.4K 
[TXT]hdllookuptable.p2020-07-29 09:43 1.4K 
[TXT]hdlmakecodegendir.p2020-07-29 09:43 250  
[TXT]hdlmulticoeffmultiply.p2020-07-29 09:43 1.4K 
[TXT]hdlmultiply.p2020-07-29 09:43 321  
[TXT]hdlmultiplycomplexcomplex.p2020-07-29 09:43 511  
[TXT]hdlmultiplycomplexreal.p2020-07-29 09:43 238  
[TXT]hdlmultiplycsd.p2020-07-29 09:43 1.6K 
[TXT]hdlmultiplyfactoredcsd.p2020-07-29 09:43 1.3K 
[TXT]hdlmultiplypowerof2.p2020-07-29 09:43 1.0K 
[TXT]hdlmultiplyrealreal.p2020-07-29 09:43 382  
[TXT]hdlmux.p2020-07-29 09:43 2.9K 
[TXT]hdlnewsignal.p2020-07-29 09:43 516  
[TXT]hdlonebitaddsub.p2020-07-29 09:43 2.4K 
[TXT]hdloutportsignals.p2020-07-29 09:43 204  
[TXT]hdlpngen.p2020-07-29 09:43 2.3K 
[TXT]hdlportdatatype.p2020-07-29 09:43 215  
[TXT]hdlprinttargetcodegenheaders.p2020-07-29 09:43 1.7K 
[TXT]hdlregsignal.p2020-07-29 09:43 327  
[TXT]hdlrelop.p2020-07-29 09:43 1.6K 
[TXT]hdlresetsignals.p2020-07-29 09:43 160  
[TXT]hdlringcounter.p2020-07-29 09:43 240  
[TXT]hdlsafeinput.p2020-07-29 09:43 420  
[TXT]hdlsaturate.p2020-07-29 09:43 228  
[TXT]hdlsequentialcontext.p2020-07-29 09:43 211  
[TXT]hdlserializer.p2020-07-29 09:43 448  
[TXT]hdlsetcurrentclock.p2020-07-29 09:43 253  
[TXT]hdlsetcurrentclockenable.p2020-07-29 09:43 335  
[TXT]hdlsetcurrentreset.p2020-07-29 09:43 251  
[TXT]hdlsetorextractbits.p2020-07-29 09:43 399  
[TXT]hdlsetpackagename.p2020-07-29 09:43 177  
[TXT]hdlsetparameter.p2020-07-29 09:43 191  
[TXT]hdlsetsignaltable.p2020-07-29 09:43 206  
[   ]hdlsetuptoolpath.m2018-01-29 22:00 2.0K 
[DIR]hdlshared_gui/2021-01-21 13:21 -  
[DIR]hdlshared_soc/2021-01-21 13:10 -  
[TXT]hdlshiftregister.p2020-07-29 09:43 238  
[TXT]hdlsignalassignment.p2020-07-29 09:43 2.1K 
[TXT]hdlsignalcomplex.p2020-07-29 09:43 295  
[TXT]hdlsignalfindname.p2020-07-29 09:43 276  
[TXT]hdlsignalforward.p2020-07-29 09:43 256  
[TXT]hdlsignalhandle.p2020-07-29 09:43 243  
[TXT]hdlsignalimag.p2020-07-29 09:43 459  
[TXT]hdlsignaliscomplex.p2020-07-29 09:43 281  
[TXT]hdlsignalisdouble.p2020-07-29 09:43 319  
[TXT]hdlsignalname.p2020-07-29 09:43 359  
[TXT]hdlsignalnext.p2020-07-29 09:43 201  
[TXT]hdlsignalrate.p2020-07-29 09:43 169  
[TXT]hdlsignalsetvtype.p2020-07-29 09:43 205  
[TXT]hdlsignalsizes.p2020-07-29 09:43 297  
[TXT]hdlsignalsltype.p2020-07-29 09:43 190  
[TXT]hdlsignaltypeconvert.p2020-07-29 09:43 441  
[TXT]hdlsignalvector.p2020-07-29 09:43 364  
[TXT]hdlsignalvtype.p2020-07-29 09:43 221  
[TXT]hdlsignedtounsigned_dtc.p2020-07-29 09:43 519  
[TXT]hdlsliceconcat.p2020-07-29 09:43 659  
[TXT]hdlsub.p2020-07-29 09:43 1.1K 
[TXT]hdlsubsub.p2020-07-29 09:43 600  
[TXT]hdlsumofelements.p2020-07-29 09:43 3.3K 
[TXT]hdlsynthtoolenum.p2020-07-29 09:43 293  
[TXT]hdltapdelay.p2020-07-29 09:43 624  
[TXT]hdltypeconvert.p2020-07-29 09:43 232  
[TXT]hdlunaryminus.p2020-07-29 09:43 1.4K 
[TXT]hdluniqueentityname.p2020-07-29 09:43 301  
[TXT]hdluniquename.p2020-07-29 09:43 359  
[TXT]hdluniqueprocessname.p2020-07-29 09:43 264  
[TXT]hdlunitdelay.p2020-07-29 09:43 739  
[TXT]hdlvalidatestruct.p2020-07-29 09:43 223  
[TXT]hdlvectorblockdatatype.p2020-07-29 09:43 234  
[TXT]hdlvectorconstantassign.p2020-07-29 09:43 781  
[TXT]hdlvectorconstantspecialassign.p2020-07-29 09:43 903  
[TXT]hdlverilogmode.p2020-07-29 09:43 414  
[TXT]hdlverilogtimescale.p2020-07-29 09:43 148  
[TXT]hdlvhdlmode.p2020-07-29 09:43 405  
[TXT]hdlwordsize.p2020-07-29 09:43 549  
[TXT]hdlwritescripts.p2020-07-29 09:43 1.3K 
[TXT]isAdderFullPrecision.p2020-07-29 09:43 276  
[TXT]isCommUSRPInstalled.p2020-07-29 09:43 125  
[TXT]isNativeFloatingPointMode.p2020-07-29 09:43 212  
[TXT]isTargetFloatingPointMode.p2020-07-29 09:43 146  
[TXT]makehdlconstantdecl.p2020-07-29 09:43 377  
[TXT]makehdlsignaldecl.p2020-07-29 09:43 967  
[TXT]makeverilogconstantdecl.p2020-07-29 09:43 460  
[TXT]makevhdlconstantdecl.p2020-07-29 09:43 269  
[TXT]pir.p2020-07-29 09:43 137  
[TXT]pirNetworkForFilterComp.p2020-07-29 09:43 230  
[TXT]pir_arr_factory_tc.p2020-07-29 09:43 127  
[TXT]pir_rec_factory_tc.p2020-07-29 09:43 128  
[   ]pir_udd.mexa642020-08-11 23:07 63K 
[TXT]pirgetvtype.p2020-07-29 09:43 419  
[TXT]pirhdlnewsignal.p2020-07-29 09:43 657  
[DIR]private/2021-01-21 13:17 -  
[TXT]resourceLog.p2020-07-29 09:43 298  
[TXT]uniquifyClockParams.p2020-07-29 09:43 546  
[TXT]verilogaddrealreal.p2020-07-29 09:43 1.3K 
[TXT]verilogaddrealrealbittrue.p2020-07-29 09:43 1.1K 
[TXT]verilogblockdatatype.p2020-07-29 09:43 197  
[TXT]verilogconstantvalue.p2020-07-29 09:43 1.1K 
[TXT]verilogcounter.p2020-07-29 09:43 2.1K 
[TXT]veriloggetvtype.p2020-07-29 09:43 365  
[TXT]verilogintdelay.p2020-07-29 09:43 2.0K 
[TXT]veriloglegalname.p2020-07-29 09:43 97  
[TXT]veriloglegalnamersvd.p2020-07-29 09:43 1.2K 
[TXT]verilogmultiplyrealreal.p2020-07-29 09:43 1.0K 
[TXT]verilogportdatatype.p2020-07-29 09:43 280  
[TXT]verilogringcounter.p2020-07-29 09:43 1.8K 
[TXT]verilogsaturate.p2020-07-29 09:43 1.4K 
[TXT]verilogsetorextractbits.p2020-07-29 09:43 784  
[TXT]verilogshiftregister.p2020-07-29 09:43 2.0K 
[TXT]verilogsubcomplexcomplex.p2020-07-29 09:43 153  
[TXT]verilogsubcomplexreal.p2020-07-29 09:43 154  
[TXT]verilogsubrealreal.p2020-07-29 09:43 1.3K 
[TXT]verilogsubrealrealbittrue.p2020-07-29 09:43 1.1K 
[TXT]verilogsubsubrealreal.p2020-07-29 09:43 928  
[TXT]verilogsubsubrealrealbittrue.p2020-07-29 09:43 925  
[TXT]verilogtapdelay.p2020-07-29 09:43 1.4K 
[TXT]verilogtypeconvert.p2020-07-29 09:43 2.4K 
[TXT]verilogunitdelay.p2020-07-29 09:43 1.5K 
[TXT]verilogvectorblockdatatype.p2020-07-29 09:43 186  
[TXT]verilogvectorportdatatype.p2020-07-29 09:43 261  
[TXT]vhdladdcomplexcomplex.p2020-07-29 09:43 149  
[TXT]vhdladdcomplexreal.p2020-07-29 09:43 150  
[TXT]vhdladdrealreal.p2020-07-29 09:43 1.1K 
[TXT]vhdladdrealrealbittrue.p2020-07-29 09:43 1.1K 
[TXT]vhdlblockdatatype.p2020-07-29 09:43 201  
[TXT]vhdlconstantvalue.p2020-07-29 09:43 1.5K 
[TXT]vhdlcounter.p2020-07-29 09:43 2.2K 
[TXT]vhdlcreateaggregate.p2020-07-29 09:43 911  
[TXT]vhdlentityinit.p2020-07-29 09:43 229  
[TXT]vhdlgetvtype.p2020-07-29 09:43 406  
[TXT]vhdlintdelay.p2020-07-29 09:43 2.3K 
[TXT]vhdlisstdlogicvector.p2020-07-29 09:43 381  
[TXT]vhdllegalname.p2020-07-29 09:43 271  
[TXT]vhdllegalnamersvd.p2020-07-29 09:43 866  
[TXT]vhdlmultiplyrealreal.p2020-07-29 09:43 1.0K 
[TXT]vhdlnzeros.p2020-07-29 09:43 220  
[TXT]vhdlpackageaddtypedef.p2020-07-29 09:43 188  
[TXT]vhdlpackageinit.p2020-07-29 09:43 291  
[TXT]vhdlportdatatype.p2020-07-29 09:43 254  
[TXT]vhdlringcounter.p2020-07-29 09:43 1.7K 
[TXT]vhdlsaturate.p2020-07-29 09:43 1.4K 
[TXT]vhdlsetorextractbits.p2020-07-29 09:43 893  
[TXT]vhdlshiftregister.p2020-07-29 09:43 2.0K 
[TXT]vhdlsubrealreal.p2020-07-29 09:43 1.1K 
[TXT]vhdlsubrealrealbittrue.p2020-07-29 09:43 1.1K 
[TXT]vhdlsubsubrealreal.p2020-07-29 09:43 807  
[TXT]vhdlsubsubrealrealbittrue.p2020-07-29 09:43 1.0K 
[TXT]vhdltapdelay.p2020-07-29 09:43 1.5K 
[TXT]vhdltypeconvert.p2020-07-29 09:43 2.8K 
[TXT]vhdlunitdelay.p2020-07-29 09:43 1.5K 
[TXT]vhdlvectorblockdatatype.p2020-07-29 09:43 568  
[TXT]vhdlvectorportdatatype.p2020-07-29 09:43 447