%% Verify HDL Design With Large Data Set Using SystemVerilog DPI Test Bench
% This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
%
% In certain applications,  simulation of a large number of samples is required to verify the HDL code generated by HDL Coder(TM) 
% for your algorithm. For instance, these applications require a large number of samples for algorithm verification :
%
% a) Calculation of radar astronomy frequency channels using a polyphase filter bank.
%
% b) Obtaining the Bit Error Rate (BER) from a Viterbi decoder in a communications system.
%
% c) Pixel-streaming video processing algorithms on high-resolution video.
%
% Generating an HDL test bench to verify such a design is time consuming because the coder must simulate the model in Simulink to capture the test bench data. 
% 
% A faster generated test bench alternative is the HDL Verifier(TM) SystemVerilog DPI test bench. The SystemVerilog DPI test bench does not require a Simulink 
% simulation, so for large data sets it generates a test bench in a shorter time than the HDL test bench.
%
% HDL Verifier(TM) SystemVerilog DPI test bench integrates with Simulink Coder(TM) to export a Simulink system as generated C code inside a 
% SystemVerilog component with a Direct Programming Interface (DPI). Within the DPI-C component the stimuli is generated and applied to the 
% C subsystem and also applied to the generated HDL code for the Simulink system. The test bench compares the output of the HDL simulation with the output of the DPI-C component
% to verify the HDL design.
%
% <<hdlcoder_DPIC_testbench_concept.png>> 
%
% Copyright 2016 The MathWorks, Inc.
%% Polyphase Filter Bank
%
% Polyphase filter bank is a widely used technique to reduce inaccuracy in FFT due to leakage and scalloping losses. 
% Polyphase filter bank produces a flatter response as compared to a normal DFT by suppressing out-of-band signals significantly.
% 
% The model is a Polyphase Filter Bank which consists of a filter and an FFT that processes 16 samples at
% a time. See <docid:dsp_ug#example-PolyphaseFilterBankHDLExample>
% for more information about the Polyphase Filter Bank.
%
modelname = 'hdlcoder_DPIC_testbench';
open_system(modelname);

%% Set up the Model
% The InitFcn callback(Model Properties > Callbacks > InitFcn) sets up the model. In this example, a 512-point 
% FFT with a four tap filter for each band is used. The dsp.Channelizer object is used to generate the coefficients.
% 
% The algorithm requires 512 filters (one filter for each band). For a vector input of 16 samples the filter implementation shares 16 filters, 32 times.
% The input data consists of two sine waves, 200KHz and 250 KHz.

%% Generate HDL Code, HDL Test Bench, and SystemVerilog DPI Test Bench
% Use a temporary directory for the generated files:
%
%   workingdir = tempname;
%
% Check the PolyphaseFilterBank subsystem for HDL code generation compatibility:
%
%   checkhdl('hdlcoder_DPIC_testbench/PolyPhaseFilterBank','TargetDirectory',workingdir);
%
% Run the following command to generate HDL code:
%
%   makehdl('hdlcoder_DPIC_testbench/PolyPhaseFilterBank','TargetDirectory',workingdir);
%
% Run the following command to generate the test bench:
%
%   makehdltb('hdlcoder_DPIC_testbench/PolyPhaseFilterBank','TargetDirectory',workingdir);
%
% This will generate an HDL test bench by simulating the model in Simulink and then capturing the test bench data. 
% 
% Run the following command to generate SystemVerilog DPI test bench:
%   
%   HDLSimulator = 'ModelSim'; % Supported Simulator Options = 'ModelSim', 'Incisive', 'VCS', 'Vivado'
%
%   makehdltb('hdlcoder_DPIC_testbench/PolyPhaseFilterBank','TargetDirectory',workingdir, 'GenerateSVDPITestBench', HDLSimulator, 'GenerateHDLTestBench', 'Off');
%
% This command generates a SystemVerilog test bench without running a Simulink simulation. Instead of a simulation, the code exports
% the Simulink system as generated C code inside a SystemVerilog component. The test bench verifies the output data by comparing it with the output of the HDL design.
% The makehdltb function also generates simulator-specific scripts for
% compilation and simulation. 
%
% SystemVerilog DPI test bench can be used to verify HDL designs of both target languages - VHDL and Verilog.
%
% Alternatively, you can set SystemVerilog DPI test bench options on the 'HDL Code Generation > Test Bench' pane in
% Configuration Parameters. 
%
% <<hdlcoder_tb_options.png>> 
%
%% Generated SystemVerilog DPI Test Bench Artifacts
% When you request a SystemVerilog DPI test bench, the coder generates the following artifacts:
% 
% a.) PolyPhaseFilterBank_dpi_tb.sv - This is the SystemVerilog test bench that verifies the HDL code.
%
% b.) PolyPhaseFilterBank_dpi_tb.do - This is the macro file that Mentor Graphics ModelSim(R) uses to compile the HDL code and run the test
% bench simulation.
%
% Based on the selected simulator, the coder generates a different file for
% compilation and test bench simulation. For instance, if you select 'Incisive',
% the coder generates 'PolyPhaseFilterBank_dpi_tb.sh' for compilation and simulation on Cadence Incisive(R).

%% (Optional) Generate HDL Code Coverage Report and Database
% To instrument the HDL Simulator to generate a HDL code coverage report and database, either:
%
% a.) On the 'HDL Code Generation > Test Bench' pane, select the check box labeled 'HDL code coverage'.
%
% b.) When you call 'makehdltb', set 'HDLCodeCoverage' to 'on'. For example:
%
%   makehdltb('hdlcoder_DPIC_testbench/PolyPhaseFilterBank','TargetDirectory',workingdir, 'GenerateSVDPITestBench', HDLSimulator, 'GenerateHDLTestBench', 'Off', 'HDLCodeCoverage', 'On');
% 
% The HDL code coverage artifacts are generated in the source directory after the test bench is simulated.
%
%% Generation Time Comparison of HDL Test Bench and SystemVerilog DPI Test Bench
% The simulation time of the model is set in the pre-load callback (Model Properties > Callbacks > PreLoadFcn)
%
%   simTime = 1000;
% 
% The sampling frequency is 2e+6 Hz, which means that the simulation to generate the HDL testbench collects 2e+9 samples. 
%
% For certain applications, it takes more samples to obtain the right frequency from the polyphase filter. 
% An increase in required simTime would also increase the time required to generate an HDL test bench. 
%
% A solution for such applications is to use the SystemVerilog DPI test bench. The generation time for the test bench 
% remains the same no matter how many samples your test scenario requires.
%
% You can increase the Simulation Time by changing the 'simTime' variable.
% For instance to generate an HDL test bench for 2e+12 samples, set:
%
%   simTime = 1000000;
%
% The table shows a comparison of time taken (in seconds) for generation of HDL test bench and SystemVerilog 
% DPI test bench for increasing numbers of samples (from 2e+9 to 2e+15) :

columns = {'NumberOfSamples';'GenerationTimeHDLTestBench';'GenerationTimeSystemVerilogDPITestbench'};
numSamples = [2e9;2e10;2e11;2e12;2e13;2e14;2e15];
HDLTBtime= [10;12;59;504;4994;52200;505506];
DPICTBtime=[47;47;47;47;47;47;47];
CompareTestBenchTimes = table(numSamples,HDLTBtime,DPICTBtime,'VariableNames',columns);
disp(CompareTestBenchTimes);
%%
% A log plot of generation time for both these test bench
% types with respect to the Number of samples, shows
% that while HDL test bench requires more generation time with an
% increase in the number of samples, generation time for the SystemVerilog DPI test bench remains 
% constant irrespective of the number of samples.

loglog(numSamples,HDLTBtime,'b-o', numSamples,DPICTBtime, 'r-o' );
xlim([2e09 2e15]);
legend('HDL Test Bench','SystemVerilog DPI Test Bench','Location','northwest');
xlabel('Number Of Samples');
ylabel('Generation time (in seconds)');
close_system(modelname,0);
%% Conclusion
% While HDL test bench is very efficient for a small number of samples,
% if your test scenario requires a large number of samples, HDL Verifier(TM)
% SystemVerilog DPI test bench provides faster test bench generation.
%%
%
%
displayEndOfDemoMessage(mfilename)

