%% Getting Started with Multicycle Path Constraint Generation
% This example shows how to use the |'MulticyclePathInfo'| property
% value pair to generate information needed to create Multicycle Path
% constraints for a multirate design.

% Copyright 2009-2012 The MathWorks, Inc.

%% Overview of Multicycle Paths
% In a multirate system not all registers operate at the highest frequency
% in the system. Many registers may operate at different rates which are
% lower than the maximum rate. Because of this, paths exist between some
% source and destination register pairs which can be allowed to have a
% longer signal propagation time than one clock period. This is referred to
% as a _multicycle path_ , because the system will operate correctly even
% if the signal on this path takes more than one clock cycle to propagate
% from source to destination register.
%
% A _multicycle path constraint_ is a timing exception to the synthesis
% tool. It tells the synthesis tool that the signal driven by the source
% register can take longer than the default one clock cycle to arrive at
% the destination register. The _path multiplier_ in a multicycle path
% constraint is essentially the number of clock cycles the signal can take
% to propagate from source to destination register. It is important to note
% that a path multiplier is relative to a clock. In a system with multiple
% synchronous clocks, a multicycle path may exist between registers which
% are not driven by a common clock. The path multiplier must be given
% relative to a specific clock.
%
% Multicycle path constraints relax timing constraints on your system. In
% some cases, multicycle paths can increase your peak operating frequency
% if your critical path lies in a multicycle path. They can also allow
% synthesis to reduce the area of a design since more time is available for
% the given path.
%
% Refer to your synthesis tool's documentation for a more information on
% multicycle paths and multicycle path constraints.

%% Multirate and Multicycle Paths in HDL Coder(TM)
% HDL Coder implements multirate via a single clock and
% pulsed clock enables. A timing controller is inserted into the HDL
% code and creates clock enables at the rates and phases required by the
% Simulink design. These clock enables are propagated throughout the system
% and control the rate of the registers in the design. This is a "global"
% timing controller for the whole system. The global timing controller is
% instantiated in the top level HDL code.
%
% In some cases (filter blocks) additional "local" timing controllers are
% inserted in smaller sections of the system. These local timing
% controllers are driven by the global timing controller.
%
% HDL Coder has the ability to analyze your multirate design
% and generate information about what multicycle paths exist in your
% design and their respective path multipliers. Set the
% |'MulticyclePathInfo'| property value pair to |'on'| when generating HDL
% code. This will produce a text file in your specified code generation
% directory called |_DUT__constraints.txt| where |_DUT_| is the name of the
% system chosen for HDL Code generation.
%
% The generated constraint text file has all the information
% required by popular synthesis tools. Each path constraint in the
% generated file indicates the *FROM* (or source) register in a multicycle
% path, the *TO* (or destination) register, the path multiplier, and the
% relative clock. Because HDL Coder implements multirate with a
% single clock, so the relative clock is always the system clock.
%
% You can use the generated constraint file information to create
% multicycle path constraints in the format desired by your synthesis tool.

%% A Simple Example
% Here is a simple model of a direct-form transposed FIR polyphase
% decimator. This filter has 32 taps and decimates by a factor of 4. The
% filter internals implement full precision arithmetic.

modelname = 'hdlfirtdecim_multicycle';
topname = 'Subsystem';
open_system(modelname);
open_system([modelname, '/', topname]);

%% Create a Temporary Directory to Work In
% First you need to create a temporary directory to work in.

currentdir = pwd;
workingdir = tempname;
mkdir(tempdir,strrep(workingdir,tempdir,''));
cd(workingdir);

%% Generate HDL and Multicycle Path Information
% This command creates the VHDL files and the |Subsystem_constraints.txt|
% file which indicates the multicycle paths in the design. In this small
% design there are 50 multicycle paths.
makehdl([modelname, '/', topname], 'MulticyclePathInfo', 'on');

%% Examining the Multicycle Paths
% Let's look at one of the multicycle paths that is reported in the
% |Subsystem_constraints.txt| file. The first constraint is:
%
% FROM : Subsystem.slowreg0_out1(7:0);
% TO : Subsystem.delay_line_out1<0>(15:0);
% PATH_MULT : 4;
% RELATIVE_CLK : source, Subsystem.clk;
%
% This indicates that a multicycle path exists between the register
% following the top Downsample block and the first register in the
% transpose add-and-delay line. The path multiplier here is four, which
% means the signal has four clock cycles to propagate from the |slowreg0|
% register through the gain block and two adders to the |delay_line|
% register. Given the arithmetic operations on this path, it would be
% useful to report this path as a multicycle path constraint to the
% synthesis tool.

%% Synthesis Results
% To see the effect of multicycle path constraints on the synthesized
% design, it is necessary to synthesize both with and without multicycle
% path constraints.
%
% Using the above model, in our tests without multicycle path constraints
% synthesis estimates the maximum clock frequency at 139 MHz without
% register retiming. When multicycle path constraints are used, the maximum
% clock frequency increases to 165 MHz. When multicycle path constraints
% were used, fewer flip-flops were needed : 228 vs 301.
%
% When retiming is used the results are more dramatic. In this scenario,
% synthesis estimates the clock frequency at 192 MHz without multicycle
% paths and 288 MHz with multicycle paths. With multicycle path constraints
% and retiming, the critical path in the design actually moved into the
% timing controller and does not run through the arithmetic logic. In
% addition, the multicycle path constraints yield nearly 50% fewer
% flip-flops in the design versus without multicycle path constraints when
% retiming is used in both cases.
%
% These test are based on a Xilinx(R) Virtex-4 xc4vsx35 in the -10 speed
% grade.
%
% You can see how, for even this small example, using multicycle path
% constraints can dramatically affect the speed of your design.

%% Conclusion
% In this example you learned how to use the |'MulticyclePathInfo'|
% property value pair and multicycle path constraints to improve the
% synthesized design speed.

cd(currentdir);

displayEndOfDemoMessage(mfilename)