FIL Frame To Pixels

Convert frame-based video to pixel stream for FPGA-in-the-loop

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  • Library:

  • Vision HDL Toolbox / I/O Interfaces

  • FIL Frame To Pixels block

Description

The FIL Frame To Pixels block performs the same frame-to-pixel conversion as the Frame To Pixels block. In addition, you can configure the width of the output vector to be a single pixel, a line, or an entire frame. The block returns control signals in vectors of the same width as the pixel data. This optimization makes more efficient use of the communication link between the FPGA board and your Simulink® simulation when using FPGA-in-the-loop (FIL). To run FPGA-in-the-loop, you must have an HDL Verifier™ license.

When you generate a programming file for a FIL target in Simulink, the tool creates a model to compare the FIL simulation with your Simulink design. For Vision HDL Toolbox™ designs, the FIL block in that model replicates the pixel-streaming interface to send one pixel at a time to the FPGA. You can modify the autogenerated model to use the FIL Frame To Pixels and FIL Pixels To Frame blocks to improve communication bandwidth with the FPGA board by sending one frame at a time. For how to modify the autogenerated model, see FPGA-in-the-Loop.

Specify the same video format and vector size for the FIL Frames To Pixels block and the FIL Pixels To Frame block.

Ports

Input

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Full image specified as a (Active pixels per line)-by-(Active video lines)-by-N matrix. Height and width are the dimensions of the active image specified in Video format. N is the Number of components used to express a single pixel.

Data Types: single | double | int | uint | Boolean | fixed point

Output

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Image pixels, returned as a matrix of M-by-Number of pixels values, where M is the width of the Output vector format. There are N data ports, where N is the Number of components. The data type is the same as the data type of frame.

When you use multipixel streaming, the FIL DUT has Number of pixels data ports. You must split the output matrix into Number of pixels row vectors of length M for the FIL DUT input ports. For details, see FPGA-in-the-Loop Simulation with Multipixel Streaming.

Similarly, when you use multicomponent-multipixel streaming, the FIL DUT has Number of pixels×Number of components data ports. Split the output matrix for each component into Number of pixels row vectors of length M for the FIL DUT input ports.

Data Types: single | double | int | uint | Boolean | fixed point

First pixel in a horizontal line of a frame, returned as a Boolean vector of M values.

For multipixel streaming, hStartOut applies to the pixel with the lowest index in the corresponding column.

Data Types: Boolean

Last pixel in a horizontal line of a frame, returned as a Boolean vector of M values.

For multipixel streaming, hEndOut applies to the pixel with the highest index in the corresponding column.

Data Types: Boolean

First pixel in the first (top) line of a frame, returned as a Boolean vector of M values.

For multipixel streaming, vStartOut applies to the pixel with the lowest index in the corresponding column.

Data Types: Boolean

Last pixel in the last (bottom) line of a frame, returned as a Boolean vector of M values.

For multipixel streaming, vEndOut applies to the pixel with the highest index in the corresponding column.

Data Types: Boolean

Valid pixel indicator, returned as a Boolean vector of M values.

For multipixel streaming, the pixels in the corresponding column are either all valid or all invalid.

Data Types: Boolean

Parameters

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Number of values used to represent each pixel. Each pixel can have 1, 3, or 4 components. Set this parameter to 1 for grayscale video. Set this parameter to 3 for color video, for example, {R,G,B} or {Y,Cb,Cr}. Set this parameter to 4 to use color with an alpha channel for transparency.

To process multicomponent streams for blocks that do not support multicomponent input, replicate the block for each component. The pixelcontrol bus for all components is identical, so you can connect the ctrl output of the Frame To Pixels block to each replicated block.

Number of pixels in each column of the output matrix, specified as 1, 4, or 8.

Each data port returns a M-by-Number of pixels matrix. You must split this matrix into Number of pixels row vectors of length M for input to the FIL DUT. For details, see FPGA-in-the-Loop Simulation with Multipixel Streaming.

Size of the vector used to communicate with the FPGA subsystem. The block returns input pixels and control signals in vectors of the same length. The block calculates the length of the vectors based on the Video format parameter.

  • Pixel — Return scalar values for pixel and control signals.

  • Line — Return (Total pixels per line)-by-1 vectors.

  • Frame — Return (Total pixels per line × Total video lines)-by-1 vectors.

A larger value results in faster communication between the FPGA board and Simulink. Choose the largest option that the I/O and memory resources on your board can support.

For multipixel streaming, specify one of these options for output size.

  • Pixel — Return a 1-by-(Number of pixels) vector of pixel values, and scalar control signals that apply to all the pixels in each vector.

  • Line — Return a (Total pixels per line/Number of pixels)-by-Number of pixels matrix of pixel values, and a vector of control signals of length (Total pixels per line)/(Number of pixels).

  • Frame — Return a (Total pixels per line × Total video lines/Number of pixels)-by Number of pixels matrix of pixel values and a vector of control signals of length (Total pixels per line × Total video lines)/Number of pixels.

Dependencies

When Number of pixels and Number of components are both greater than 1, you must set Output vector format to Frame.

Dimensions of active and inactive regions in a video frame. To select a predefined format, select from the Video format list. The actual frame dimensions are displayed in the Video Format Parameters section. For a custom format, select Custom, and then specify the dimensions as integers.

The dimensions are defined in the diagram.

Note

The sample time of your video source must match the total number of pixels in the frame of your Frame To Pixels block. The total number of pixels is Total pixels per line × Total video lines, so set the sample time to this value.

Video FormatActive Pixels Per LineActive Video LinesTotal Pixels Per LineTotal Video LinesStarting Active LineEnding Active LineFront PorchBack Porch
240p320240 40232412404438
480p6404808005253651516 144
480pH7204808585253351216122
576p7205768646254762212132
720p1280720165075025744110260
768p102476813448061077724296
1024p128010241688106642106548360
1080p (default)192010802200112542112188192
1200p160012002160125050124964496
2KCinema204810802750112542112163963
4KUHDTV384021604400225042220188472
8KUHDTV7680432088004500424361881032
CustomUser-
defined		User-
defined		User-
defined		User-
defined		User-
defined		User-
defined		User-
defined		User-
defined

When using a custom format, the values you enter for the active and inactive dimensions of the image must add up to the total frame dimensions. If you specify a format that does not conform to these rules, the block reports an error.

  • For the horizontal direction, Total pixels per line must be greater than or equal to Front porch + Active pixels per line. The block calculates Back porch = Total pixels per line − Front porch − Active pixels per line.

  • For the vertical direction, Total video lines must be greater than or equal to Starting active line + Active video lines − 1. The block calculates Ending active line = Starting active line + Active video lines − 1.

When using the Line Memory block, or blocks that use an internal line memory, with a custom video format, further requirements apply:

  • Active pixels per line must be greater than 1.

  • The horizontal blanking interval, or Back porch + Front porch, must meet these guidelines:

    • The total of Back porch + Front porch must be at least 2 times the largest kernel size of the algorithm in the blocks following the Frame To Pixel block. If the kernel size is less than 4, the total porch must be at least 8 pixels.

    • The Back porch must be at least 6 pixels. This parameter is the number of inactive pixels before the first valid pixel in a frame.

    For more information on blanking intervals, see Configure Blanking Intervals.

When using multipixel streaming (Number of pixels > 1) these requirements apply.

  • The video format must have horizontal dimensions divisible by the Number of pixels parameter value. The horizontal dimensions are set by these parameters: Active pixels per line, Total pixels per line, Front porch, and Back porch. Standard video protocols 480p, 720p, 1080p, and 4k UHD support Number of pixels equal to 4 or 8.

  • The minimum input frame size for multipixel streaming (either 4 or 8 pixels) is 18 rows-by-32 columns.

  • Choose your kernel size and Active pixels per line such that (Active pixels per line)/(Number of pixels) is at least the kernel width.

Model Examples

FPGA-in-the-Loop Simulation with Vision HDL Toolbox Blocks

FPGA-in-the-Loop Simulation with Vision HDL Toolbox Blocks

Modify the generated FPGA-in-the-loop (FIL) model for more efficient simulation of the Vision HDL Toolbox™ streaming video protocol.

Extended Capabilities

See Also

Blocks

Topics

Introduced in R2015a

Vision HDL Toolbox Documentation

Support