Dead logic detection helps you to identify:
Model design errors.
Extraneous model elements.
Model elements that should be executed, but are not.
In this example, you analyze a fuel rate controller model to determine if the model contains dead logic. Dead logic detection finds the incorrect variable value that causes a transition condition in a Stateflow® chart to remain inactive.
Open the model.
sldvdemo_fuelsys_logic_simple
Ensure that the current folder is writable.
Configure dead logic detection.
On the Design Verifier tab, in the Mode section, select Design Error Detection.
Select Error Detection Settings.
In the Configuration Parameter dialog box, select Dead logic (partial). Clear Run exhaustive analysis. Click OK.
Click Detect Design Errors.
The results dialog box shows that there are 2/109 objectives that are dead logic.
Create an analysis report. From the results inspector window, click HTML.
Scroll to the Dead Logic section. The table lists two instances of dead logic.
In the Description column, one of the dead logic
instances is the false
condition of press <
zero_thresh
. The dead logic result indicates that in the
simulation, the false
condition was not executed. This logic
is part of the Sens_Failure_Counter.INC
transition.
Click the Model Item link. Simulink highlights the transition in the chart.
The logical statement controlling the transition is
speed==0 & press < zero_thresh
Return to the report. Scroll to the Constraints section.
The value of the input control logic/Input Data "press"
is
constrained from 0 through 2. Click the link to open the input in the Model
Explorer.
Select the Model Workspace in the Model Explorer. In the
contents table, select zero_thresh
. The value of
zero_thresh
is 250.
Given the constrained value of press
, it is
always less than zero_thresh
and
therefore, the false
condition is
never exercised.
Change the value of zero_thresh
to 0.250.
Reanalyze the model. On the Design Verifier tab, click Detect Design Errors.
In the new results, the objective is no longer dead logic.