Triggered Subsystem

Subsystem whose execution is triggered by external input

Library:
Simulink / Ports & Subsystems
HDL Coder / Ports & Subsystems

Description

The Triggered Subsystem block is a Subsystem block preconfigured as a starting point for creating a subsystem that executes each time the control signal has a trigger value.

Use Triggered Subsystem blocks to model:

A task that runs with the detection of a trigger value.
An interrupt from I/O hardware.
A processor request to handle an exception or error.

Ports

Input

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`In` — Signal input to a subsystem block
scalar | vector | matrix

Placing an Inport block in a subsystem block adds an external input port to the block. The port label matches the name of the Inport block.

Use Inport blocks to get signals from the local environment.

`Trigger` — Control signal input to a subsystem block
scalar

Placing a Trigger block in a subsystem block adds an external input port to the block.

Output

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`Out` — Signal output from a subsystem
scalar | vector | matrix

Placing an Outport block in a subsystem block adds an output port from the block. The port label on the subsystem block is the name of the Outport block.

Use Outport blocks to send signals to the local environment.

Model Examples

Triggered Subsystems

Triggered subsystems and describes the different trigger types. A triggered subsystem is executed for a single time step whenever the trigger port transitions from false to true in a specified direction. The transition of the trigger port may occur when the direction of the transition is rising, falling, or both rising and falling. A rising transition occurs when the trigger signal transitions from zero or below to a positive value. A falling transition occurs when the trigger signal transitions from zero or above to a negative value.

Open Model

Block Priority

What happens when blocks are assigned different priorities. The block priority affects the order in which the blocks are executed. You can set the block priority through the Block Properties dialog.

Open Model

Block Priority

What happens when blocks are assigned different priorities. The block priority affects the order in which the blocks are executed. You can set the block priority through the Block Properties dialog.

Open Model

Bang-Bang Control Using Temporal Logic

Use Stateflow® to model a bang-bang temperature control system for a boiler. The boiler dynamics are modeled in Simulink®.

Open Model

Modeling Engine Timing Using Triggered Subsystems

Model a four-cylinder spark ignition internal combustion engine from the throttle to the crankshaft output. We used well-defined physical principles supplemented, where appropriate, with empirical relationships that describe the system's dynamic behavior without introducing unnecessary complexity.

Open Model

Engine Timing Model with Closed Loop Control

Enhance a version of the open-loop engine model described in Modeling Engine Timing Using Triggered Subsystems. This model, sldemo_enginewc, contains a closed-loop and shows the flexibility and extensibility of Simulink® models. In this enhanced model, the objective of the controller is to regulate engine speed with a fast throttle actuator, such that changes in load torque have minimal effect. This is easily accomplished in Simulink by adding a discrete-time PI controller to the engine model.

Open Model

Block Characteristics

Data Types	`Boolean^[a]` \| `bus^[a]` \| `double^[a]` \| `enumerated^[a]` \| `fixed point^[a]` \| `half^[a]` \| `integer^[a]` \| `single^[a]` \| `string^[a]`
Direct Feedthrough	`no`
Multidimensional Signals	`limited^[a]`
Variable-Size Signals	`limited^[a]`
Zero-Crossing Detection	`no`
^[a] Actual data type or capability support depends on block implementation.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual code generation support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For information about best practices, restrictions, and how you can use the trigger signal as a clock with the TriggerAsClock property, see Using Triggered Subsystems for HDL Code Generation (HDL Coder).

HDL Architecture

Architecture Description

Module (default) Generate code for the subsystem and the blocks within the subsystem.

Architecture	Description
`Module` (default)	Generate code for the subsystem and the blocks within the subsystem.
`BlackBox`	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
`No HDL`	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

BlackBox

Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code.

The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.

No HDL

Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

Black Box Interface Customization

For the BlackBox architecture, you can customize port names and set attributes of the external component interface. See Customize Black Box or HDL Cosimulation Interface (HDL Coder).

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is `inherit`. See also AdaptivePipelining (HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is `inherit`. See also BalanceDelays (HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is `inherit`. See also ClockRatePipelining (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `off`. See also DistributedPipelining (HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is `none`. See also DSPStyle (HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is `inherit`. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming (HDL Coder).

Target Specification

This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type support depends on block implementation.

Documentation

Triggered Subsystem

Description