Signal Specification

Specify desired dimensions, sample time, data type, numeric type, and other attributes of signal

Library:
Simulink / Signal Attributes
HDL Coder / Signal Attributes

Description

The Signal Specification block allows you to specify the attributes of the signal connected to its input and output ports. If the specified attributes conflict with the attributes specified by the blocks connected to its ports, Simulink^® software displays an error when it compiles the model. For example, at the beginning of a simulation, if no conflict exists, Simulink eliminates the Signal Specification block from the compiled model. In other words, the Signal Specification block is a virtual block. It exists only to specify the attributes of a signal and plays no role in the simulation of the model.

You can use the Signal Specification block to ensure that the actual attributes of a signal meet desired attributes. For example, suppose that you and a colleague are working on different parts of the same model. You use Signal Specification blocks to connect your part of the model with your colleague's. If your colleague changes the attributes of a signal without informing you, the attributes entering the corresponding Signal Specification block do not match. When you try to simulate the model, you get an error.

You can also use the Signal Specification block to ensure correct propagation of signal attributes throughout a model. However, if some blocks have unspecified attributes for the signals they accept or output, the model does not have enough information to propagate attributes correctly. In these cases, the Signal Specification block can provide the information Simulink needs. Using the Signal Specification block also helps speed up model compilation when blocks are missing signal attributes.

The Signal Specification block supports signal label propagation.

Ports

Input

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`Port_1` — Input signal
scalar | vector | matrix | N-D array

Input signal whose attributes to check, specified as a scalar, vector, matrix, or N-D array. The block checks the attributes of the input signal against the desired attributes you specify in the block dialog box. If the attributes do not match, the block generates an error.

Output

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`Port_1` — Output signal
scalar | vector | matrix | N-D array

Output signal is the input signal when all attributes of the signal match those specified in the dialog box. If the attributes do not match, the block generates an error.

Parameters

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`Minimum` — Minimum value for range checking
`[]` (default) | scalar

Specify the minimum value for the block output as a finite real double scalar value.

Note

If you specify a bus object as the data type for this block, do not set the minimum value for bus data on the block. Simulink ignores this setting. Instead, set the minimum values for bus elements of the bus object specified as the data type. For information on the Minimum property of a bus element, see Simulink.BusElement.

Simulink uses this value to perform:

Simulation range checking (see Specify Signal Ranges)
Automatic scaling of fixed-point data types

Programmatic Use

Block Parameter: OutMin

Type: character vector

Values: scalar

Default:

'[
									]'

`Maximum` — Maximum value for range checking
`[]` (default) | scalar

Specify the maximum value for the block output as a finite real double scalar value.

Note

If you specify a bus object as the data type for this block, do not set the maximum value for bus data on the block. Simulink ignores this setting. Instead, set the maximum values for bus elements of the bus object specified as the data type. For information on the Maximum property of a bus element, see Simulink.BusElement.

Simulink uses this value to perform:

Simulation range checking (see Specify Signal Ranges)
Automatic scaling of fixed-point data types

Programmatic Use

Block Parameter: OutMax

Type: character vector

Values: scalar

Default:

'[
									]'

`Data type` — Output data type
`Inherit: auto` (default) | `double` | `single` | `half` | `int8` | `uint8` | `int16` | `uint16` | `int32` | `uint32` | `int64` | `uint64` | `boolean` | `fixdt(1,16)` | `fixdt(1,16,0)` | `fixdt(1,16,2^0,0)` | `Enum: <class name>` | `Bus: <object name>` | `string` | `<data type expression>`

Specify the desired output data type. If the data type of the input signal does not match the value you specify, the block generates an error.

Click the Show data type assistant button to display the Data Type Assistant, which helps you set the data type attributes. For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Value:

'Inherit: auto' | 'double' | 'single' | 'half' | 'int8' |
									'uint8' | 'int16' | 'uint16' | 'int32' | 'uint32' | 'int64' |
									'uint64' | 'boolean' | 'fixdt(1,16,0)' | 'fixdt(1,16,2^0,0)' |
									'Enum: <class name>' | 'Bus: <object name>' |
									'string' | <data type expression>

Default: 'Inherit: auto'

`Lock output data type setting against changes by the fixed-point tools` — Prevent fixed-point tools from overriding Output data type
`off` (default) | `on`

Select this parameter to prevent the fixed-point tools from overriding the Output data type you specify on the block. For more information, see Use Lock Output Data Type Setting (Fixed-Point Designer).

Programmatic Use

Block Parameter: LockScale

Type: character vector

Values: 'off' | 'on'

Default: 'off'

`Require nonvirtual bus` — Accept only nonvirtual bus signals
`off` (default) | `on`

If you specify a bus object as the data type, use this parameter to specify whether to accept only nonvirtual bus signals.

off — Specifies that a signal must come from a virtual bus.
on — Specifies that a signal must come from a nonvirtual bus.

Dependencies

To enable this parameter, set Data type to one of these values:

Bus: <object name>
<data type expression> that specifies a bus object

Programmatic Use

Block Parameter: BusOutputAsStruct

Type: character vector

Value: 'off' | 'on'

Default: 'off'

`Unit (e.g., m, m/s^2, N*m)` — Physical unit of the input signal to the block
`inherit` (default) | `<Enter unit>`

Specify the physical unit of the input signal to the block. To specify a unit, begin typing in the text box. As you type, the parameter displays potential matching units. For a list of supported units, see Allowed Unit Systems.

To constrain the unit system, click the link to the right of the parameter:

If a Unit System Configuration block exists in the component, its dialog box opens. Use that dialog box to specify allowed and disallowed unit systems for the component.
If a Unit System Configuration block does not exist in the component, the model Configuration Parameters dialog box displays. Use that dialog box to specify allowed and disallowed unit systems for the model.

Programmatic Use

Block Parameter: Unit

Type: character vector

Values: 'inherit' | '<Enter unit>'

Default: 'inherit'

`Dimensions (-1 for inherited)` — Dimensions of input and output signals
`-1` (default) | `n` | `[m n]`

Specify the dimensions of the input and output signals.

-1 — Specifies that signals inherit dimensions.
n — Specifies a vector of width n.
[m n] — Specifies a matrix with m rows and n columns.

Programmatic Use

Block Parameter: Dimensions

Type: character vector

Values: '-1' | n |

[m
									n]

Default: '-1'

`Variable-size signal` — Allow signal to be variable-size, fixed-size, or both
`Inherit` (default) | `No` | `Yes`

Specify the signal to be of variable-size, fixed size, or both.

Inherit — Allows variable-size and fixed-size signals.
No — Does not allow variable-size signals.
Yes — Allows only variable-size signals.

Dependencies

When the signal is a variable-size signal, the Dimensions parameter specifies the maximum dimensions of the signal.

If you specify a bus object, the simulation allows variable-size signals only with a disabled bus object.

Programmatic Use

Block Parameter: VarSizeSig

Type: character vector

Values: 'Inherit' | 'No' | 'Yes'

Default: 'Inherit'

`Sample time (-1 for inherited)` — Time interval between samples
`-1` (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time for more information.

Programmatic Use

Parameter: SampleTime

Type: character vector

Values: Any valid sample time

Default: '-1'

`Signal type` — Complexity of signal
`auto` (default) | `real` | `complex`

Specify the complexity of the input and output signals.

auto — Accepts either real or complex as the numeric type.
real — Specifies the numeric type as a real number.
complex — Specifies the numeric type as a complex number.

Programmatic Use

Parameter: SignalType

Type: character vector

Values: 'auto' | 'real' | 'complex'

Default: 'auto'

Model Examples

Modeling Objects with Identical Dynamics Using For Each Subsystem

Model multiple objects with identical dynamics using the For Each Subsystem. The number of objects is parameterized by the length of the input signal.

Open Model

Block Characteristics

Data Types	`Boolean` \| `bus` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single` \| `string`
Direct Feedthrough	`no`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a pass-through implementation.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Documentation

Signal Specification

Description

Ports

Input

Port_1 — Input signal scalar | vector | matrix | N-D array

Output

Port_1 — Output signal scalar | vector | matrix | N-D array

Parameters

Minimum — Minimum value for range checking [] (default) | scalar

Programmatic Use

Maximum — Maximum value for range checking [] (default) | scalar

Programmatic Use

Data type — Output data type Inherit: auto (default) | double | single | half | int8 | uint8 | int16 | uint16 | int32 | uint32 | int64 | uint64 | boolean | fixdt(1,16) | fixdt(1,16,0) | fixdt(1,16,2^0,0) | Enum: <class name> | Bus: <object name> | string | <data type expression>

Programmatic Use

Lock output data type setting against changes by the fixed-point tools — Prevent fixed-point tools from overriding Output data type off (default) | on

Programmatic Use

Require nonvirtual bus — Accept only nonvirtual bus signals off (default) | on

Dependencies

Programmatic Use

Unit (e.g., m, m/s^2, N*m) — Physical unit of the input signal to the block inherit (default) | <Enter unit>

Programmatic Use

Dimensions (-1 for inherited) — Dimensions of input and output signals -1 (default) | n | [m n]

Programmatic Use

Variable-size signal — Allow signal to be variable-size, fixed-size, or both Inherit (default) | No | Yes

Dependencies

Programmatic Use

Sample time (-1 for inherited) — Time interval between samples -1 (default) | scalar | vector

Programmatic Use

Signal type — Complexity of signal auto (default) | real | complex

Programmatic Use

Model Examples

Modeling Objects with Identical Dynamics Using For Each Subsystem

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Topics

Simulink Documentation

Support

`Port_1` — Input signal
scalar | vector | matrix | N-D array

`Port_1` — Output signal
scalar | vector | matrix | N-D array

`Minimum` — Minimum value for range checking
`[]` (default) | scalar

`Maximum` — Maximum value for range checking
`[]` (default) | scalar

`Lock output data type setting against changes by the fixed-point tools` — Prevent fixed-point tools from overriding Output data type
`off` (default) | `on`

`Require nonvirtual bus` — Accept only nonvirtual bus signals
`off` (default) | `on`

`Unit (e.g., m, m/s^2, N*m)` — Physical unit of the input signal to the block
`inherit` (default) | `<Enter unit>`

`Dimensions (-1 for inherited)` — Dimensions of input and output signals
`-1` (default) | `n` | `[m n]`

`Variable-size signal` — Allow signal to be variable-size, fixed-size, or both
`Inherit` (default) | `No` | `Yes`

`Sample time (-1 for inherited)` — Time interval between samples
`-1` (default) | scalar | vector

`Signal type` — Complexity of signal
`auto` (default) | `real` | `complex`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.