Detect Change

Detect change in signal value

Library:
Simulink / Logic and Bit Operations
HDL Coder / Logic and Bit Operations

Description

The Detect Change block determines if an input signal does not equal its previous value. The initial condition determines the initial value of the previous input U/z.

This block supports only discrete sample times.

Ports

Input

expand all

`Port_1` — Input signal
signal value

Input signal, specified as a scalar, vector, or matrix.

Output

expand all

`Port_1` — Output signal
0 | 1

Output signal, true (equal to 1) when the input signal does not equal its previous value; false (equal to 0) when the input signal equals its previous value.

Parameters

expand all

`Initial condition` — Initial condition for the previous input
0 (default) | scalar | vector

Set the initial condition for the previous input U/z.

Programmatic Use

Block Parameter: vinit

Type: character vector

Values: scalar | vector

Default:'0'

`Input processing` — Specify sample- or frame-based processing
`Elements as channels (sample based)` (default) | `Columns as channels (frame based)`

Specify whether the block performs sample- or frame-based processing:

Columns as channels (frame based) — Treat each column of the input as a separate channel (frame-based processing).
Note
Frame-based processing requires a DSP System Toolbox™ license.
For more information, see Sample- and Frame-Based Concepts (DSP System Toolbox).
Elements as channels (sample based) — Treat each element of the input as a separate channel (sample-based processing).

Use Input processing to specify whether the block performs sample- or frame-based processing. The block accepts frame-based signals for the input u. All other input signals must be sample-based.

Input Signal u	Input Processing Mode	Block Works?
Sample based	Sample based	Yes
Frame based	Sample based	No, produces an error
Sample based	Frame based	Yes
Frame based	Frame based	Yes

For more information about these two processing modes, see Sample- and Frame-Based Concepts (DSP System Toolbox).

Programmatic Use

Block Parameter: InputProcessing

Type: character vector

Values:

'Columns as channels
                        (frame based)'

'Elements as channels (sample
                        based)'

Default:

'Elements as channels
                        (sample based)'

`Output data type` — Data type of the output
`boolean` (default) | `uint8`

Set the output data type to boolean or uint8.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'boolean' | 'uint8'

Default: 'boolean'

Model Examples

Detect Change in Signal Values

Detect a change in signal values using the Detect Change block.

Open Model

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`yes`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

Detect Change

Description

Ports

Input

`Port_1` — Input signal
signal value

Output

`Port_1` — Output signal
0 | 1

Parameters

`Initial condition` — Initial condition for the previous input
0 (default) | scalar | vector

Programmatic Use

`Input processing` — Specify sample- or frame-based processing
`Elements as channels (sample based)` (default) | `Columns as channels (frame based)`

Programmatic Use

`Output data type` — Data type of the output
`boolean` (default) | `uint8`

Programmatic Use

Model Examples

Detect Change in Signal Values

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

Documentation

Detect Change

Description

Ports

Input

Port_1 — Input signal signal value

Output

Port_1 — Output signal 0 | 1

Parameters

Initial condition — Initial condition for the previous input 0 (default) | scalar | vector

Programmatic Use

Input processing — Specify sample- or frame-based processing Elements as channels (sample based) (default) | Columns as channels (frame based)

Programmatic Use

Output data type — Data type of the output boolean (default) | uint8

Programmatic Use

Model Examples

Detect Change in Signal Values

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

`Port_1` — Input signal
signal value

`Port_1` — Output signal
0 | 1

`Initial condition` — Initial condition for the previous input
0 (default) | scalar | vector

`Input processing` — Specify sample- or frame-based processing
`Elements as channels (sample based)` (default) | `Columns as channels (frame based)`

`Output data type` — Data type of the output
`boolean` (default) | `uint8`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.