Demux

Library:
Simulink / Commonly Used Blocks
Simulink / Signal Routing
HDL Coder / Commonly Used Blocks
HDL Coder / Signal Routing

Ports

Input

`Port_1` — Accept nonbus vector signal to extract and output signals from
real or complex values of any nonbus data type supported by Simulink^®

Vector input signal from which the Demux block selects scalar signals or smaller vectors.

Output

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`Port_1` — Output signals extracted from input vector signal
nonbus signal with real or complex values of any data type supported by Simulink

Output signals extracted from the input vector. The output signal ports are ordered from top to bottom. See Port Location After Rotating or Flipping for a description of the port order for various block orientations.

Parameters

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`Number of outputs` — Number of outputs
2 (default) | scalar | vector

Specify the number and, optionally, the dimensionality of each output port. If you do not specify the dimensionality of the outputs, the block determines the dimensionality of the outputs.

The value can be a scalar specifying the number of outputs or a vector whose elements specify the widths of the block output ports. The block determines the size of its outputs from the size of the input signal and the value of the Number of outputs parameter.

If you specify a scalar for the Number of outputs parameter and all of the output ports are connected, as you draw a new signal line close to output side of a Demux block, Simulink adds a port and updates the Number of outputs parameter.

For an input vector of width n, here is what the block outputs.

Parameter Value	Block outputs...	Examples and Comments
`p = n`	`p` scalar signals	If the input is a three-element vector and you specify three outputs, the block outputs three scalar signals.
`p > n`	Error	This value is not supported.
`p < n` `n mod p = 0`	`p` vector signals each having `n/p` elements	If the input is a six-element vector and you specify three outputs, the block outputs three two-element vectors.
`p < n` `n mod p = m`	`m` vector signals each having `(n/p)+1` elements and `p-m` signals having `n/p`elements	If the input is a five-element vector and you specify three outputs, the block outputs two two-element vector signals and one scalar signal.
`[p`₁`p`₂`... p`_m`]` `p`₁`+p`₂`+...+p`_m`=n` `p`_i`> 0`	`m` vector signals having widths `p₁`, `p₂`, ... `p_m`	If the input is a five-element vector and you specify `[3, 2]` as the output, the block outputs three of the input elements on one port and the other two elements on the other port.
An array that has one or more of `m` elements with a value of `-1`, which specifies that Simulink infers the size for the element. For example, suppose that you have a four-element array with a total width of 14 and you specify the parameter to be `[p`₁`p`₂`-1p`₄`]`. The value for the third element (the `-1` element) is `14 -(p₁ + p₂ + p₄)`	`m` vector signals	If `p`_i is greater than zero, the corresponding output has width `p`_i. If `p`_i is -1, the width of the corresponding output is computed dynamically.
`[p`₁`p`₂`... p`_m`]` `p`₁`+p`₂`+...+p`_m`!=n` `p`_i`= > 0`	Error	This value is not supported

If you specify the number of outputs that is smaller than the number of input elements, the block distributes the elements as evenly as possible over the outputs. For examples, see Extract Vector Elements and Distribute Evenly Across Outputs and Extract Vector Elements Using the Demux Block.

Programmatic Use

Block Parameter: Outputs

Type: scalar or vector

Values: character vector

Default: {'2'} or vector

`Display option` — Displayed block icon
`bar` (default) | `none`

By default, the block icon is a solid bar of the block foreground color. To display the icon as a box containing the block type name, select none.

Programmatic Use

Block Parameter: Display option

Type: character vector

Values: 'bar' | 'none'

Default: 'bar'

Model Examples

Extract Vector Elements and Distribute Evenly Across Outputs

Use the Demux block to distribute an input signal evenly over the desired number of outputs.

Open Model

Extract Vector Elements Using the Demux Block

When using the Demux block to extract and output elements from a vector input, you can use -1 in a vector expression to indicate that the block dynamically sizes the corresponding port.

Open Model

Create Mux Signal and Extract Elements

Create a mux signal and extract elements from the mux signal.

Open Model

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.

Documentation

Demux

Description

Ports

Input

`Port_1` — Accept nonbus vector signal to extract and output signals from
real or complex values of any nonbus data type supported by Simulink^®

Output

`Port_1` — Output signals extracted from input vector signal
nonbus signal with real or complex values of any data type supported by Simulink

Parameters

`Number of outputs` — Number of outputs
2 (default) | scalar | vector

Programmatic Use

`Display option` — Displayed block icon
`bar` (default) | `none`

Programmatic Use

Model Examples

Extract Vector Elements and Distribute Evenly Across Outputs

Extract Vector Elements Using the Demux Block

Create Mux Signal and Extract Elements

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Topics

Simulink Documentation

Support

Documentation

Demux

Description

Ports

Input

Port_1 — Accept nonbus vector signal to extract and output signals from real or complex values of any nonbus data type supported by Simulink®

Output

Port_1 — Output signals extracted from input vector signal nonbus signal with real or complex values of any data type supported by Simulink

Parameters

Number of outputs — Number of outputs 2 (default) | scalar | vector

Programmatic Use

Display option — Displayed block icon bar (default) | none

Programmatic Use

Model Examples

Extract Vector Elements and Distribute Evenly Across Outputs

Extract Vector Elements Using the Demux Block

Create Mux Signal and Extract Elements

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Topics

Simulink Documentation

Support

`Port_1` — Accept nonbus vector signal to extract and output signals from
real or complex values of any nonbus data type supported by Simulink^®

`Port_1` — Output signals extracted from input vector signal
nonbus signal with real or complex values of any data type supported by Simulink

`Number of outputs` — Number of outputs
2 (default) | scalar | vector

`Display option` — Displayed block icon
`bar` (default) | `none`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.