FPGA-in-the-Loop

Test designs in real hardware

Creating an FPGA-in-the-loop link between the simulator and the board enables you to:

  • Verify HDL implementations directly against algorithms in Simulink® or MATLAB®.

  • Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.

  • Integrate existing HDL code with models under development in Simulink or MATLAB.

Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.

After you download a board support package, select a simulation workflow. See FPGA-in-the-Loop Simulation Workflows. To learn how FIL simulation works, see FPGA-in-the-Loop Simulation.

Apps

FPGA-in-the-Loop WizardGenerate an FPGA-in-the-loop (FIL) block or System object from existing HDL files

Objects

hdlverifier.FILSimulation FIL simulation with MATLAB

Functions

programFPGA Load programming file onto FPGA

Blocks

FIL SimulationSimulate HDL code on FPGA hardware from Simulink

Topics

Overview

FPGA-in-the-Loop Simulation Workflows

Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

FPGA-in-the-Loop Simulation

FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

FIL Requirements and Preparation

Prepare DUT For FIL Interface Generation

DUT guidelines for FIL simulation of blocks and System objects.

Download FPGA Board Support Package

The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, data capture, or MATLAB AXI master.

Set Up FPGA Design Software Tools

Set the MATLAB path to Xilinx®, Microsemi®, and Intel® software.

Guided Hardware Setup

Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop.

Manual Hardware Setup

Describes the steps necessary to prep hardware and hardware tools for FIL.

Generate FIL Interface from Legacy Code

Block Generation with the FIL Wizard

Generate a FPGA-in-the-Loop block from existing HDL source files, then include the FPGA implementation in a Simulink simulation.

System Object Generation with the FIL Wizard

Generate a FPGA-in-the-Loop System object from existing HDL source files, then include the FPGA implementation in a MATLAB simulation.

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.

Verify Digital Up-Converter Using FPGA-in-the-Loop

This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.

Generate FIL System Object from MATLAB Code (requires HDL Coder license)

FIL Simulation with HDL Workflow Advisor for MATLAB

Generate an FPGA-in-the-loop System object and test bench using HDL Workflow Advisor.

Generate FIL Block from Simulink Model (requires HDL Coder license)

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)

Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

FIL Simulation with HDL Workflow Advisor for Simulink

Generate an FPGA-in-the-loop model using HDL Workflow Advisor.

Troubleshooting

Troubleshooting FIL

Fixes for common error messages and issues.

Featured Examples

FPGA-in-the-Loop Simulation Using MATLAB System Object

FPGA-in-the-Loop Simulation Using MATLAB System Object

Use a MATLAB System object and a FPGA to verify a register transfer level (RTL) design of a Fast Fourier Transform (FFT) of size 8 written in Verilog. The FFT is commonly used in digital signal processing to produce frequency distribution of a signal.

Open Example
Verify Viterbi Decoder Using MATLAB System Object and FPGA-in-the-Loop

Verify Viterbi Decoder Using MATLAB System Object and FPGA-in-the-Loop

Use MATLAB® System objects and FPGA-in-the-Loop to simulate a Viterbi decoder implemented in VHDL on a FPGA.

Open Example
Video Processing Acceleration Using FPGA-in-the-Loop

Video Processing Acceleration Using FPGA-in-the-Loop

Uses FPGA-in-the-Loop (FIL) simulation to accelerate a video processing simulation with Simulink® by adding an FPGA. The process shown analyzes a simple system that sharpens an RGB video input at 24 frames per second.

Open Model
Accelerating Communications System Simulation Using FPGA-in-the-Loop

Accelerating Communications System Simulation Using FPGA-in-the-Loop

Uses FPGA-in-the-Loop (FIL) simulation to accelerate part of a communications system. The application uses the Viterbi Algorithm to decode a convolutional encoded random stream that is BPSK modulated, sent through an AWGN channel, and then demodulated. Using a sample-by-sample approach leads to a modest speedup over normal Simulink® simulation, while using the "Process as Frames" option leads to further speedup.

Open Model
Algorithm Verification with a FIL Source Block

Algorithm Verification with a FIL Source Block

Verify an HDL design quickly and efficiently using FPGA-in-the-Loop (FIL). The test bench is synthesized together with the Design Under Test (DUT), the result is downloaded to an FPGA board, and the test is run with FIL. Using FIL for this process enables high speed generation and processing of test stimulus, with results returned to Simulink for analysis. This example shows how these tasks are accomplished for an image processing use case.

Open Model

HDL Verifier Documentation

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