Introduction

The Simscape HDL Workflow Advisor converts the Simscape plant model to an HDL-compatible implementation model from which you generate HDL code. In some cases, the Simscape plant model might not be compatible for implementation model generation. In such cases, you first modify the Simscape plant model and then run the Advisor.

This example illustrates how to modify a permanent magnet synchronous motor model for compatibility with Simscape HDL Workflow Advisor. The model is continuous time and contains many nonlinear components. You modify this model to a discrete-time switched linear model and then run the Simscape HDL Workflow Advisor.

Permanent Magnet Synchronous Motor Model

The permanent magnet synchronous motor model is a physical system in Simscape. To open the model, run this command:

open_system('ee_pmsm_drive')

Save this model as ee_pmsm_drive_original.slx.

open_system('ee_pmsm_drive_original')
set_param('ee_pmsm_drive_original','SimulationCommand','Update')

The model contains a Permanent Magnet Synchronous Machine (PMSM) and inverter sized that you can use in a typical hybrid vehicle. The inverter is connected to the vehicle battery. To see how the model works, simulate the model.

sim('ee_pmsm_drive_original')
open_system('ee_pmsm_drive_original/Scope')

This model is a continuous time system. To use this model with Simscape HDL Workflow Advisor, convert the model into a discrete system. You then modify the model to use blocks that are compatible for the Simscape to HDL workflow.

Convert Continuous-Time Model to Fixed-Step Discrete Model

1. Configure the solver options for HDL code generation by using a Solver Configuration (Simscape) block. In the block parameters:

2. Modify the Solver settings of the model. On the Modeling tab, click Model Settings. On the Solver pane:

3. Modify the display settings of your model. On the Debug tab, select Information Overlays > Sample Time > Colors. Review the Sample Time Legend for blocks that have a sample time other than Ts, or run at a continuous time scale. Double-click the Step block and set the Sample time to Ts.

4. For faster simulation, ignore the zero-sequence parameters of the PMSM. Double-click the Permanent Magnet Synchronous Motor block and set Zero Sequence to Exclude.

The model is now a fixed-step discrete system. Simulate the model and compare the Torque Demand and Motor Torque signals in the Simulation Data Inspector. The signals differ by more than the tolerance levels toward the end of simulation but are within acceptable limits.

You use a two-step process to convert the Simscape plant model to a HDL-compatible implementation model:

Replace Nonlinear Simscape Blocks with Equivalent Simulink Implementation

1. To make the Simscape plant model HDL-Compatible, identify the presence of any nonlinear components or blocks in the model:

simscape.findNonlinearBlocks('ee_pmsm_drive_original')

Found network that contains nonlinear equations in the following blocks:
    {'ee_pmsm_drive_original/Permanent Magnet Synchronous Motor'}

The number of linear or switched linear networks in the model is 0.
The number of nonlinear networks in the model is 1.

ans =

  1x1 cell array

    {'ee_pmsm_drive_original/Permanent Magnet Synchronous Motor'}

The Simscape plant model has a nonlinear block, which is the PMSM block.

2. The PMSM block, Encoder block, Gmin resistor, and Motor & Load Inertia block are replaced with Simulink blocks that perform the equivalent algorithm.

To implement the Electrical Interface block, you use Controlled Current Sources.

The interface to the PMSM is isolated from the implementation. To implement the PMSM by using Simulink blocks, you use Electrical Equations and Mechanical Equations. Inside the Park Transform and Inverse Park Transform blocks, eliminate the Sine and Cosine blocks.

Identify Simscape Blocks that Run on FPGA and Restructure Simscape Model

The ee_pmsm_drive_singleSL model illustrates how you modify the original model ee_pmsm_drive_original and prepare the model for readiness with Simscape HDL Workflow Advisor.

1. To modify the Simscape model for compatibility with HDL implementation model generation, identify the part of the Simscape algorithm that you want to run on the FPGA. In this example, you can run the three-phase inverter, electrical interface, PWM, and the Permanent Magnet Synchronous Motor (Simulink) on the FPGA.

2. After blocks to run on the FPGA have been identified, the blocks are placed inside a top-level subsystem. This subsystem is the DUT (Design Under Test) and contains blocks you run on the FPGA after generating the HDL implementation model. Afer running the Simscape HDL Workflow Advisor, this subsystem is replaced with the HDL algorithm. This part of the Simscape model must run at the fastest sample rate. Rate Transition blocks are added to upsample the design.

3. To save resource usage on the target hardware, Data Type Conversion blocks are added to convert the model to use single data types.

The ee_pmsm_drive_singleSL model shows how these blocks are placed inside a top-level subsystem Subsystem1, which is the DUT. The blocks inside the subsystem are running at a faster rate.

load_system('ee_pmsm_drive_singleSL')
set_param('ee_pmsm_drive_singleSL','SimulationCommand','update')
open_system('ee_pmsm_drive_singleSL/Subsystem1')

In the ee_pmsm_drive_singleSL model, the three-phase inverter and electrical interface are placed inside the Simscape Inverter and Interface subsystem.

open_system('ee_pmsm_drive_singleSL/Subsystem1/Simscape Inverter and Interface')

Modify Permanent Magnet Synchronous Motor Subsystem for HDL Compatibility

The preceding section describes the changes that have been applied to the masked subsystem, Permanent Magnet Synchronous Motor (Simulink).

1. The Integrator with Wrapped State (Discrete or Continuous) block is not compatible for HDL code generation. This block has been replaced with a Wrapped State DTI subsystem.

PMSMSubsystem = 'ee_pmsm_drive_singleSL/Subsystem1/Permanent Magnet Synchronous Motor (Simulink)';
open_system(PMSMSubsystem, 'force')

open_system([PMSMSubsystem, '/Wrapped State DTI'])

2. To reduce the FPGA area footprint for the:

open_system([PMSMSubsystem, '/Park Transform'])

open_system([PMSMSubsystem, '/Inverse Park Transform'])

3. For the Discrete-Time Integrator blocks inside this subsystem, the Sample time is set to -1, Gain value to Ts, and Integrator method to Accumulation:Forward Euler. You can view these block parameters programmatically by running these commands.

blockDTI = find_system(PMSMSubsystem, 'LookUnderMasks', 'on', ...
                                'blocktype', 'DiscreteIntegrator');
 for  n  =  1:numel(blockDTI)
    Integpath = blockDTI(n);
    Integname = get_param(Integpath, 'Name');
    stime = num2str(get_param(blockDTI{n}, 'SampleTime'));
    gval = num2str(get_param(blockDTI{n}, 'gainval'));
    integmethod = num2str(get_param(blockDTI{n}, 'IntegratorMethod'));
    disp('----------------------------------------------------')
    disp(Integpath)
    disp(['Sample time: ', stime, '    Gain: ', gval, ...
                    '    Integration method: ', integmethod])
 end
disp('----------------------------------------------------')

----------------------------------------------------
    {'ee_pmsm_drive_singleSL/Subsystem1/Permanent Magnet...'}

Sample time: -1    Gain: Ts    Integration method: Accumulation: Forward Euler
----------------------------------------------------
    {'ee_pmsm_drive_singleSL/Subsystem1/Permanent Magnet...'}

Sample time: -1    Gain: Ts    Integration method: Accumulation: Forward Euler
----------------------------------------------------

Prepare Model and Run Simscape HDL Workflow Advisor

To the top level of the model:

This figure illustrates the top level of the model with the above changes.

open_system('ee_pmsm_drive_singleSL')

To open the Simscape HDL Workflow Advisor, run the sschdladvisor function for your model:

sschdladvisor('ee_pmsm_drive_singleSL')

To generate the implementation model, in the Simscape HDL Workflow Advisor, leave the default settings and then run the tasks. To open the implementation model, in the Generate implementation model task, click the link.

Reconfigure Implementation Model for HDL Code Generation

In this example, the implementation model has been modified for deployment to Speedgoat FPGA I/O platforms. The model is resaved as gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL.

To reconfigure the single-precision implementation model for HDL code generation:

1. Run the hdlsetup function on the model.

hdlsetup('gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL')

2. The model solver setting, Fixed-step size, is modified to Ts/5 because the default Number of solver iterations is 5.

3. The Subsystem1 block contains blocks that you run on the FPGA. The Simscape Inverter and Interface subsystem is replaced with the HDL Subsystem block. The HDL Subsystem block contains the HDL Algorithm that contains the HDL implementation of the Simscape algorithm. To see the HDL algorithm implementation, open this block.

model_name = 'gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL';
dut_name = 'gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL/Subsystem1';
load_system(model_name)
set_param(model_name,'SimulationCommand','Update')
open_system([dut_name, '/HDL Subsystem'])

open_system([dut_name, '/HDL Subsystem/HDL Algorithm'])

4. The HDL Algorithm Subsystem has a Valid Out signal. The Permanent Magnet Synchronous Motor (Simulink) subsystem is placed inside an Enabled Subsystem and the vs_LL input port is connected to the Valid Out signal.

open_system(dut_name)

5. Move the block inside the subsystem that originally contained the Simscape algorithm to the top level of the model.

This figure illustrates the top level of the model with the above changes.

open_system(model_name)

Generate HDL Code

Before you generate HDL code, to compare the output of the generated model after code generation with the modified Simscape plant model, specify validation model generation.

hdlset_param(model_name, 'GenerateValidationModel', 'on');

To learn more, see Generated Model and Validation Model.

To generate HDL code, run this command:

makehdl('gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL/HDL Subsystem')

By default, HDL Coder generates VHDL code. To generate Verilog code, run this command:

makehdl('gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL/HDL Subsystem', 'TargetLanguage', 'Verilog')

The code generator saves the generated HDL code and the validation model in the hdlsrc folder. The generated code is saved as HDL_Subsystem_tc.vhd. To see the resource usage information of your design, view the Code Generation Report.

To open the validation model, after you generate HDL code, open the gm_gmStateSpaceHDL_ee_pmsm_drive_GenerateHDL_vnl.slx model.

Deploy Permanent Magnet Synchronous Motor to Speedgoat FPGA I/O Modules

In the HDL implementation model, Subsystem1 contains blocks you run on the FPGA. You can run the HDL Workflow Advisor on this Subsystem to deploy the HDL algorithm onto FPGA boards in Speedgoat target platforms. For an example, see Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules.