Language-Specific File Extension Parameters

Verilog file extension

Specify the file name extension for generated Verilog^® files.

Settings

Default: .v

This field specifies the file name extension for generated Verilog files.

Dependency

To enable this option, set the target language to Verilog. You can specify the target language by using the Language parameter in the HDL Code Generation pane.

Command-Line Information

Property: VerilogFileExtension

Type: character vector

Default: '.v'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'VerilogFileExtension','.v')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','VerilogFileExtension','.v')
makehdl('sfir_fixed/symmetric_fir')
```

VHDL file extension

Specify the file name extension for generated VHDL^® files.

Settings

Default: .vhd

This field specifies the file name extension for generated VHDL files.

Dependency

To enable this option, set the target language to VHDL. You can specify the target language by using the Language parameter in the HDL Code Generation pane.

Command-Line Information

Property: VHDLFileExtension

Type: character vector

Default: '.vhd'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'VHDLFileExtension','.vhd')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','VHDLFileExtension','.vhd')
makehdl('sfir_fixed/symmetric_fir')
```

Documentation