Specify a black box implementation for the Model block when you already have legacy or manually-written HDL code. HDL Coder™ generates the HDL code that is required to interface to the referenced HDL code.
Code is generated with the following assumptions:
Every HDL entity or module requires clock, clock enable, and reset ports. Therefore, these ports are defined for each generated entity or module.
Use of Simulink® data types is assumed. For VHDL® code,
port data types are assumed to be STD_LOGIC or STD_LOGIC_VECTOR.
If you want to generate code for a multirate, multiclock DUT that includes a referenced model, see Model Referencing for HDL Code Generation.
To instantiate an HDL wrapper, or black box interface, for a referenced model:
Right-click the Model block and select HDL Code > HDL Block Properties.
In the HDL Block Properties dialog box:
For Architecture, select BlackBox.
Customize the ports and other implementation parameters. To learn more about customizing the ports, see Customize Black Box or HDL Cosimulation Interface.
Generate HDL code for your DUT subsystem.
If you run the checkhdl function to check the compatibility of
your model for HDL code generation, the function does not check the port data types
within the referenced model.
If you encounter typing or naming conflicts between vector ports when interfacing
two or more generated VHDL code modules, use the ScalarizePorts property to
generate nonconflicting port definitions. For more information, see Scalarize ports.