Debug IP Core Using FPGA Data Capture

This example uses:

Open Script

This example shows how to debug HDL Coder generated IP Core using HDL Verifier's FPGA Data Capture feature.

Requirements

  • Xilinx Zynq ZC702 evaluation kit

  • HDL Coder Support Package for Xilinx Zynq Platform

  • HDL Verifier Support Package for Xilinx FPGA Boards

  • (Optional) Embedded Coder Support Package for Xilinx Zynq Platform

  • (Optional) DSP System Toolbox

  • Follow the "Set up Zynq hardware and tools" section in HDL Coder example Getting Started with Targeting Xilinx Zynq Platform to setup ZC702 hardware.

Introduction

When you debug the generated IP Core from HDL Coder, it is useful to monitor the IP Core internal signals when it is running on the real hardware. This example shows how to use the HDL Verifier's FPGA Data Capture to capture such signals into MATLAB for debugging analysis.

Start by looking at the example model:

open_system('hdlcoder_led_blinking_data_capture');

The subsystem led_counter is the hardware subsystem targeting the FPGA fabric. Inside this subsystem, we marked several internal signals as test points. HDL Coder will route those internal signals out of the DUT and into the IP Core wrapper so that the signals can be connected to the FPGA Data Capture HDL IP.

open_system('hdlcoder_led_blinking_data_capture/led_counter');

Generate HDL IP Core

Start HDL Workflow Advisor from the model and run through the IP Core Generation workflow. For a detailed step by step guide, please refer to the example Getting Started with Targeting Xilinx Zynq Platform

1. In step 1.1., select IP Core Generation in the Target workflow. For "Target Platform", select "Xilinx Zynq ZC702 evaluation kit"

2. In step 3.1.3, under "Ports" tab check the "Enable HDL DUT port generation for test points"

3. In Step 1.3, select "FPGA Data Capture - JTAG" interface for blinkfrequency, blinkdirection, led_output, and count ports.

4. Run through the remaining workflow steps to generate HDL IP, and program the target device.

Capture and display data from IP Core

Now FPGA fabric has been programmed and running, the next step is to capture the data from the Zynq board.

First, locate the FPGA Data Capture launch script. In this example, the script is in your HDL code generation directory: hdl_prj/ip_core/led_count_ip_v1_0/fpga_data_capture/launchDataCaptureApp.m. You can also locate this script in the code generation report.

Next, run this script in MATLAB. You will need to add the directory where this script is located to the MATLAB path or change your current folder.

After executing this script, the FPGA Data Capture App is launched. You can click the "Capture Data" button to capture data from FPGA without setting up any triggers.

Alternatively, you can setup a trigger condition where led_counter==0, and trigger position of 32. Then click "Capture Data" button again.

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