Check ID:
com.mathworks.HDL.ModelChecker.runArchitectureNameChecks
Check VHDL architecture name in the generated HDL code.
This check verifies whether the architecture name is rtl when
you generate code with VHDL as the target language. This check corresponds to rule
1.A.F.1 of the industry-standard rules.
To fix this warning, click Modify Settings and the code
generator updates the VHDLArchitectureName setting to
rtl to adhere to the industry-standard rule.
Rule 1.A.F.1 of Basic Coding Practices.