Cosimulation

HDL cosimulation with Simulink^® (requires HDL Verifier™)

When you generate HDL code, you can optionally generate a Simulink model that includes an HDL Cosimulation block that runs your generated HDL code in an HDL simulator. The model also includes your original Simulink stimulus generation, behavioral model, and blocks that display or analyze output. The model compares the output of the HDL Cosimulation block against the output of the source subsystem.

Functions

makehdltb Generate HDL test bench from model or subsystem

Simulink Configuration Parameters

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Test Bench Generation Output and Postfix

Test Bench Generation Output Parameters

Test Bench Postfix Parameters

Multi-file test bench

Test Bench Inputs and Output

Clock and Reset Input Parameters for Testbench

Setup and Hold Time Parameters for Testbench

Test Bench Stimulus and Output Parameters

Topics

HDL Cosimulation (HDL Verifier)

The HDL Verifier software consists of MATLAB^® functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

Generate a Cosimulation Model

Automatically generate a Simulink model that cosimulates with your HDL simulator.

Set Up for HDL Cosimulation (HDL Verifier)

To cosimulate your HDL code with a MATLAB or Simulink design, you must first:

Automatic Verification of Generated HDL Code from Simulink (HDL Verifier)

Verify generated HDL code using a generated cosimulation model.

Choose a Test Bench for Generated HDL Code

Select a generated test bench.

Featured Examples

HDL Verifier Cosimulation Model Generation in HDL Coder™

Generate a cosimulation model in of HDL Coder and integrate the generated HDL code into an HDL Verifier™ workflow. Automation of cosimulation model generation enables seamless verification of the generated hardware design.

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Documentation