Normally, you time models from which you plan to generate code from a periodic interrupt source (for example, a hardware timer). Blocks in a periodically clocked single-rate model run at a timer interrupt rate (the base rate of the model). Blocks in a periodically clocked multirate model run at the base rate or at multiples of that rate.
Many systems must also support execution of blocks in response to events that are asynchronous with respect to the periodic timing source of the system. For example, a peripheral device might signal completion of an input operation by generating an interrupt. The system must service such interrupts, for example, by acquiring data from the interrupting device.
This topic explains how to use blocks to model and generate code for asynchronous event handling, including servicing of hardware-generated interrupts, maintenance of timers, asynchronous read and write operations, and spawning of asynchronous tasks under a real-time operating system (RTOS). This block library demonstrates integration with an example RTOS (VxWorks®). Although the blocks target an example RTOS, this chapter provides source code analysis and other information you can use to develop blocks that support asynchronous event handling for an alternative target RTOS.[1]
The next figure shows the blocks in the vxlib1
block
library.
The key blocks in the library are the Async Interrupt and Task Sync blocks. These blocks are targeted for an example RTOS (VxWorks). You can use them, with modification, to support your RTOS applications.
Note
You can use the blocks in the vxlib1
library
(Async Interrupt and Task
Sync) for simulation and code generation. These blocks provide
starting point examples to help you develop custom blocks for your
target environment.
To implement asynchronous support for an RTOS other than the
example RTOS, use the guidelines and example code are provided to
help you adapt the vxlib1
library blocks to target
your RTOS. This topic is discussed in Create a Customized Asynchronous Library.
The vxlib1
library includes blocks you can
use to
Generate interrupt-level code — Async Interrupt block
Spawn an RTOS task that calls a function call subsystem — Task Sync block
Enable data integrity when transferring data between blocks running as different tasks — Protected RT block
Use an unprotected/nondeterministic mode when transferring data between blocks running as different tasks — Unprotected RT block
The use of protected and unprotected Rate Transition blocks in asynchronous contexts is discussed in Rate Transitions and Asynchronous Blocks. For general information on rate transitions, see Time-Based Scheduling and Code Generation.
To access the example RTOS (VxWorks) block library, enter the MATLAB® command vxlib1
.
To generate an example RTOS compatible application from a model containing
vxlib1
library blocks, use the following model configuration
parameter settings for your model.
Set System target file (SystemTargetFile
) to
ert.tlc
(requires an Embedded Coder® license).
Select Generate code only
(GenCodeOnly
).
Select Generate an example main program
(GenerateSampleERTMain
).
Set Target operating system (TargetOS
) to
VxWorksExample
.
Additional information relevant to the topics in this chapter can be found in
The rtwdemo_async
model, which uses the tornado.tlc
system target file and vxlib1
block library. To
open this example, type rtwdemo_async
at the MATLAB command prompt.
The rtwdemo_async_mdlreftop
model, which uses the
tornado.tlc
system target file and
vxlib1
block library. To open this example,
type rtwdemo_async_mdlreftop
at the MATLAB command prompt.
Time-Based Scheduling and Code Generation, discusses general multitasking and rate transition issues for periodic models.
The Embedded Coder documentation
discusses the ert.tlc
system target file, including
task execution and scheduling.
For detailed information about the system calls to the example RTOS (VxWorks) mentioned in this chapter, see VxWorks system documentation on the Wind River® website.
[1] VxWorks is a registered trademark of Wind River Systems, Inc.