FIR Rate Conversion HDL Optimized

Upsample, filter, and downsample input signal and generates optimized HDL code

Library:
DSP System Toolbox HDL Support / Filtering

Description

The FIR Rate Conversion HDL Optimized block upsamples, filters, and downsamples input signals. It is optimized for HDL code generation and operates on one sample of each channel at a time. The block implements a polyphase architecture to avoid unnecessary arithmetic operations and high intermediate sample rates.

The block upsamples the input signal by an integer factor of L, applies it to a FIR filter, and downsamples the input signal by an integer factor of M.

You can use the input and output control ports for pacing the flow of samples. In the default configuration, the block uses validIn and validOut control signals. For additional flow control, you can enable a ready output signal and a request input signal.

The ready output port indicates that the block can accept a new input data sample on the next time step. When L ≥ M, you can use the ready signal to achieve continuous output data samples. If you apply a new input sample after each time the block returns ready signal as 1, the block returns a data output sample with the validOut signal set to 1 on every time step.

When you disable the ready port, you can apply a valid data sample only every ceil(L/M) time steps. For example, if:

L/M = 4/5, then you can apply a new input sample on every time step.
L/M = 3/2, then you can apply a new input sample on every other time step.

When you enable the request input port, the block returns the next output sample when therequest signal is 1 and a valid output sample is available. When you disable the request port, the block returns output samples when they are available. When no new data is available, block sets the validOut signal to 0.

You can connect the request input port to the ready output port of a downstream block.

Ports

Input

expand all

`dataIn` — Input data sample
scalar | row vector

Input data sample, specified as a scalar, or as a row vector in which each element represents an independent channel. The block accepts real or complex data.

double and single data types are supported for simulation, but not for HDL code generation.

`validIn` — Indication of valid input signal
scalar

When valid is 1 (true), the block captures the data from the dataIn port. You can apply a valid data sample every ceiling(L/M) time steps.

Data Types: Boolean

`request` — Request control signal
scalar

When the request port is 1, and an output data sample is available, the block returns that output data sample on the dataOut port and sets the validOut output signal to 1. When no new data is available, the block sets the validOut output signal to 0. When the request port is 0, the block holds available data until the request port is set to 1.

You can connect the request input port to the ready output port of a downstream block.

Dependencies

To enable this port, select the Enable request input port checkbox.

Data Types: Boolean

Output

expand all

`dataOut` — Output data sample
scalar | row vector

Output data sample, returned as a scalar or a row vector in which each element represents an independent channel.

`validOut` — Indication of valid input signal
scalar

The block sets validOut to true along with each valid data returned on the dataOut output port.

Data Types: Boolean

`ready` — Ready control signal
scalar

The block sets ready to true to indicate that it is ready for new input data on the next cycle.

You can connect the ready output port to the request input port of an upstream block.

Dependencies

To enable this port, select the Enable ready output port checkbox.

Data Types: Boolean

Parameters

expand all

Main

`Interpolation factor` — Interpolation factor
`3` (default) | positive integer

Specify a factor by which the block interpolates the input data sample.

`Decimation factor` — Decimation factor
`2` (default) | positive integer

Specify a factor by which the block decimates the input data sample.

`FIR filter coefficients` — FIR filter coefficients
`firpm(70, [0 0.28 0.32 1],[1 1 0 0])` (default) | row vector

Specify a row vector of coefficients in descending powers of z^-1.

Note

You can generate filter coefficients using Signal Processing Toolbox™ filter design functions (such as fir1). Design a lowpass filter with normalized cutoff frequency no greater than min(1/L,1/M). The block initializes internal filter states to zero.

Control Ports

`Enable ready output port` — Option to enable ready control signal
`off` (default) | `on`

Select this parameter to enable the ready port.

`Enable request input port` — Option to enable request control signal
`off` (default) | `on`

Select this parameter to enable the request port.

Data Types

`Rounding mode` — Rounding mode for fixed-point operation
`Floor` (default) | `Ceiling` | `Convergent` | `Nearest` | `Round` | `Zero`

Select a rounding mode for fixed-point operations. For more information, see Rounding mode.

`Saturate on integer overflow` — Method of overflow action
`off` (default) | `on`

Specify whether overflows saturate or wrap.

off — Overflows wrap to the appropriate value that data type can represent. For example, because 130 does not fit in a signed 8-bit integer, it wraps to -126.
on — Overflows saturate to either the minimum or maximum value that data type can represent. For example, an overflow associated with a signed 8-bit integer can saturate to -128 or 127.

`Coefficients Data Type` — FIR filter coefficients data type
`fixdt(1,16,16)` (default)

FIR filter coefficients data type, specified as a fixdt(s,wl,fl) object with signedness, word length, and fractional length properties.

`Output Data Type` — Data type of output data sample
`Inherit: Same word length as input` (default) | `Inherit via internal rule` | `fixdt(s,wl,fl)`

Specify the data type for the output data samples.

Model Examples

Downsample a Signal

Convert a signal from 48 kHz to 32 kHz using the FIR Rate Conversion HDL Optimized block.

Control Data Rate Using the Ready and Request Ports

Convert a signal from 40 MHz to 100 MHz using the FIR Rate Converter HDL Optimized block. Uses the optional request input signal and ready output signal to control the data rate. To represent a system clock rate of 200MHz, the model connects a repeating true-false signal to the request port. This configuration generates output samples at 100 MHz, i.e. every second time step. Alternatively, you can connect this port to the ready port of a downstream block.

Algorithms

expand all

The FIR Rate Conversion HDL Optimized block implements a fully parallel polyphase filter architecture. The diagram shows where the block casts the data types based on your configuration.

Delay

Because the block models HDL pipeline latency, an initial delay of several time steps exists before the block returns the first valid output data sample. The latency depends on the filter coefficients and the resampling factors. To determine the latency from the first input data sample to the first output data sample, use the validOut signal.

Performance

For an example of design performance, generate HDL for the block as configured in the Control Data Rate Using the Ready and Request Ports example. The example filter resamples at 5/2, and uses a symmetric 71-tap filter. The input samples and filter coefficients are 16 bits wide. The design is targeted to a Xilinx^® Virtex^®-6 FPGA, using Xilinx ISE synthesis and place and route tools.

After placement and routing, the design achieves 535 MHz clock frequency and uses these resources of the FPGA device.

LUT	592
FFS	979
Xilinx LogiCORE^® DSP48	15
Block RAM (16K)	0

Performance of the synthesized HDL code varies depending on your filter coefficients, FPGA target, and synthesis options.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

FIR Rate Conversion HDL Optimized

Description