HDL Code Generation

Generate HDL code from MATLAB® code and Simulink® models

You can use HDL Coder™ features to implement communications system designs on FPGAs or ASICs. You can generate synthesizable and portable VHDL® and Verilog® code, and generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code. You can generate code from Simulink or MATLAB designs. This support includes error correction and detection, modulation, filters, mathematical and signal operations, and other algorithms optimized for resource use and performance, such as the NCO HDL Optimized block. For a basic example of how to generate HDL code, see Programmable FIR Filter for FPGA.

To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.

Topics

Find Blocks That Support HDL Code Generation

Filter for blocks that support HDL code generation in the Simulink library browser and in documentation.

Wireless Communications Design for FPGAs and ASICs

Design wireless communication algorithms for hardware by using Wireless HDL Toolbox™ blocks.

Simulink Visualization Tool

Logic AnalyzerVisualize, measure, and analyze transitions and states over time

Related Information

Featured Examples

HDL Optimized QPSK Transmitter

HDL Optimized QPSK Transmitter

Optimize the QPSK transmitter modeled in commqpsktxrx.slx for HDL code generation and hardware implementation.

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HDL Optimized QPSK Receiver with Captured Data

HDL Optimized QPSK Receiver with Captured Data

Optimize the QPSK receiver modeled in QPSK Transmitter and Receiver example for HDL code generation and hardware implementation. The HDL-optimized model shows a QPSK receiver that addresses real-world communications issues like carrier recovery and timing recovery in a hardware-friendly manner.

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HDL Optimized QAM Transmitter and Receiver

HDL Optimized QAM Transmitter and Receiver

Implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation.

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HDL Code Generation for Viterbi Decoder

HDL Code Generation for Viterbi Decoder

HDL code generation support for the Viterbi Decoder block. It shows how to check, generate, and verify the HDL code you generate from a fixed-point Viterbi Decoder model. This example also discusses the settings you can use to alter the HDL code you generate.

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Airplane Tracking with ADS-B Captured Data

Airplane Tracking with ADS-B Captured Data

Implement the Automatic Dependent Surveillance - Broadcast (ADS-B) receiver for HDL code generation and hardware implementation. This example decodes ADS-B extended squitter messages which can be used to track the airplane. The HDL-optimized model in this example uses Simulink® blocks that support HDL code generation to implement the ADS-B Receiver. This example model is used for real-time processing in HW/SW Co-Design Implementation of ADS-B Transmitter/Receiver Using Analog Devices AD9361/AD9364 (Communications Toolbox Support Package for Xilinx Zynq-Based Radio), which requires the Communications Toolbox™ Support Package for Xilinx® Zynq®-Based Radio.

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Communications Toolbox Documentation

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