%% Run Workflow with Configuration Object
% This example is a generic ASIC/FPGA workflow script that targets a
% Xilinx Virtex-7 device. It uses the Xilinx Vivado synthesis tool. The
% example generates HDL code for the |sfir_fixed| model, and performs FPGA
% synthesis and analysis.
%% Before running the Workflow
% Before running the workflow, you must have the synthesis tool installed.
% Use hdlsetuptoolpath to specify the path to your synthesis tool.

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath',...
'L:\Xilinx\Vivado\2016.2\bin\vivado.bat');

%% Specify the model for running the workflow
% To run the HDL workflow with default settings for a DUT subsystem, |modelname/DUT|,
% at the command line, enter:
open_system('sfir_fixed');

%% Model HDL Parameters
% Set Model HDL parameters
hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7vx485t');
hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'ffg1761');
hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-2');

%% Workflow Configuration Settings
% * Construct the Workflow Configuration Object with default settings
% * Specify the path to your project folder. This step is optional

hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado', ...
'TargetWorkflow','Generic ASIC/FPGA');

hWC.ProjectFolder = 'C:/Temp/hdl_prj';

%% Run the workflow

hdlcoder.runWorkflow('sfir_fixed/symmetric_fir', hWC);

%%
% Copyright 2012 The MathWorks, Inc.