%% Model References: Build Model Design Using Smaller Partitions

% Copyright 2018 The MathWorks, Inc.

%% Guideline ID
% |2.4.4|

%% Severity
% _Recommended_

%% Description
% Modeling a large design hierarchically can increase code generation time.
% If you specify generation of reports such as the traceability report, the
% code generation time can further increase significantly. To avoid such
% performance issues, it is recommended that you partition your design into
% smaller partitions. Use the 
% <docid:simulink_ref#f7-2720095> block to unify a model that consists of smaller partitions.
% It also enables incremental code generation. You can generate HDL code
% for the parent model or the referenced model. To see the generated HDL code,
% in the |hdlsrc| folder, a folder is created for the parent model with a separate
% subfolder for the referenced model.
%
% When generating the HDL test bench, if the test bench consists of blocks
% that operate with a continuous sample time, you can convert the DUT to a
% referenced model. This conversion enables the DUT to run
% at a fixed-step, discrete sample time. To learn more, see 
% <docid:hdlcoder_ug#mw_c077ffa8-fb81-4b2c-ba7d-1678aac0e65f>.
%
%%
% For an example, open the model |hdlcoder_divide_parentmodel.slx|. When
% you double-click the DUT Subsystem, you see a Model block that references
% the model |hdlcoder_divide_referencedmodel|.
load_system('hdlcoder_divide_parentmodel')
set_param('hdlcoder_divide_parentmodel', 'SimulationCommand', 'Update')
open_system('hdlcoder_divide_parentmodel/DUT')
%%
% To see the referenced model, double-click the Model block:
open_system('hdlcoder_divide_parentmodel/DUT/Model')
%%
% To generate HDL code, enter this command:
%
%   makehdl('hdlcoder_divide_parentmodel/DUT')
%
% For more information, see <docid:hdlcoder_ug#bt1yaf2>.