%% Modeling for AXI4 Master Interfaces
% You can model your algorithm with Data and AXI4 Master protocol signals at the 
% DUT ports and then map the signals to AXI4 Master interfaces.

%%
% Copyright 2020 The MathWorks, Inc.

%%
% <<../axi_master_ipcore.png>>
%
% To learn how to model your DUT algorithm for AXI4 Master interface
% mapping, open this Simulink(R) model. The DUT Subsystem contains a simple 
% algorithm that reads data from the DDR and writes the data back to a different 
% address in the DDR memory.
open_system('hdlcoder_axi_master')
sim ('hdlcoder_axi_master')
%%
% Double-click the DUT Subsystem. The DDR_Access_Controller Subsystem
% models the AXI Master read and write channels and has a Simple Dual Port RAM
% that calculates the wr_data signal. If you double-click the 
% DDR_Access_Controller Subsystem, you see two Edge Detection Subsystem blocks
% that generate the two start pulses as input to each MATLAB Function block. One 
% Edge Detection Subsystem and DDR Read Controller MATLAB Function models the 
% read transaction. The other Edge Detection Subsystem and DDR Write Controller 
% MATLAB Function models the write transaction. You can modify this design to 
% model only the write transaction or the read transaction by using one Edge 
% Detection Subsystem and the corresponding MATLAB Function block. 
%
%% Read Channel
% The DDR Read Controller is modeled as a state machine with four states: INIT, IDLE, 
% READ_BURST_START, and DATA_COUNT. The INIT state initializes the read
% signals and the RAM input signals. When the start signal goes high, the state 
% machine switches to the IDLE state, and then waits for the |rd_aready| signal
% to become high. When |rd_aready| becomes high, the state machine transitions 
% to the READ_BURST_START state and the DUT starts reading data. The state machine
% then unconditionally switches to the DATA_COUNT state and continues to
% read data till |rd_avalid| goes low.
%
%% Write Channel
% The DDR Write Controller is modeled similar to the Read channel as a state machine 
% with four states : IDLE, WRITE_BURST_START, DATA_COUNT, and ACK_WAIT. The DUT
% is in the IDLE state and then switches to the WRITE_BURST_START state
% where it waits for the |wr_ready| signal. When |wr_ready| becomes high,
% the state machine switches to the DATA_COUNT state and starts writing
% data. The data is valid when |wr_valid| is high. The DUT continues to write
% data when |wr_ready| is high. As |wr_ready| becomes low, the
% state machine switches to the ACK_WAIT state and then  waits for the ready
% signal to initiate the next write transaction.
%
% To see the simplified AXI4 Master protocol in effect, simulate the model. If you
% have DSP System Toolbox(TM) installed, you can view and analyze the results in
% the Logic Analyzer.
%%
% <<../axi_master_read_waveform.png>>
%
% You can use the IP Core Generation workflow to generate an HDL IP core with the
% AXI4 Master interface. If you have HDL Verifier(TM) installed, and you use the 
% Xilinx Zynq ZC706 board, then you can integrate the IP core into the Default 
% System with External DDR3 memory access reference design.

