%% Insert Unconditional Transition State for Else Statement in HDL Code

% Copyright 2019 The MathWorks, Inc.

%% Guideline ID
% |2.9.3|

%% Severity
% _Recommended_

%% Description
% When you use Stateflow(R) charts for HDL code generation, insert
% unconditional states in the chart. The HDL code generated for such a
% chart contains an else branch with the if statement. The presence of an
% else branch prevents the third-party tool from inferring a latch when you 
% deploy the HDL code. For example, open the model
% |hdlcoder_chart_ifnelsecond|. 
open_system('hdlcoder_chart_ifnelsecond')
set_param('hdlcoder_chart_ifnelsecond', 'SimulationCommand', 'Update')
open_system('hdlcoder_chart_ifnelsecond/dut_chart')
%%
% The model contains two Stateflow Moore Charts. The chart |onlyif_chart|
% implements a simple condition that outputs out1 based on in1.
open_system('hdlcoder_chart_ifnelsecond/dut_chart/onlyif_chart')
%%
% The Chart block |ifnelse_chart| is the same as |onlyif_chart| and has an 
% unconditional transition state.
open_system('hdlcoder_chart_ifnelsecond/dut_chart/ifnelse_chart')
%%
% To generate HDL code for the DUT, run this command:
%
%   makehdl('hdlcoder_chart_ifnelsecond/dut_chart')
%%
% The HDL code generated for the |onlyif_chart| does not contain an else
% condition. Do not deploy this code to a target device because synthesis 
% tools might infer a latch.
%
% <<../if_only_chart_verilog.png>>
%
% The HDL code generated for the |ifnelse_chart| contains an else statement
% for the unconditional transition state. This code is recommended for
% deployment to the target FPGA device.
%
% <<../if_else_chart_verilog.png>>


