%% Generate Verilog for a Subsystem Within a Model  
% Generate Verilog(R) for the subsystem |symmetric_fir| within the model
% |sfir_fixed|.   

%% 
% Open the |sfir_fixed| model. 
sfir_fixed; 

%%
% The model opens in a new Simulink(R) window.  

%% 
% Generate Verilog for the |symmetric_fir| subsystem. 
makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog', ...
               'TargetDirectory', 'C:/Generate_Verilog/hdlsrc') 

%%
% The generated Verilog code for the |symmetric_fir| subsystem is saved
% in |hdlsrc\sfir_fixed\symmetric_fir.v|.  

%% 
% Close the model. 
bdclose('sfir_fixed');   



%% 
% Copyright 2012 The MathWorks, Inc.