%% Generate VHDL for the Current Model   
% This example shows how to generate VHDL for the symmetric FIR model.
%%
% Open the |sfir_fixed| model. 
sfir_fixed
%% 
% Generate HDL code for the current model with code generation options set
% to default values. 
makehdl('sfir_fixed/symmetric_fir','TargetDirectory','C:\GenVHDL\hdlsrc') 

%%
% The generated VHDL code is saved in the |hdlsrc| folder.   



%% 
% Copyright 2012 The MathWorks, Inc.