%% Generate Simulink Model from Verilog Code for Various Operators
% This example shows how you can import Verilog code that contains these operators 
% and generate the corresponding Simulink(TM) model:
% 
% * Arithmetic
% * Logical
% * XOR
% * Bitwise
% * Conditional
% * Relational
% * Concatenation

% Copyright 2018 The MathWorks, Inc.

%% Specify Input Verilog File
% Make sure that the input HDL file does not contain any syntax errors, is synthesizable,
% and uses constructs for the various operators. For example, this Verilog code shows 
% various operators.
edit('VerilogOperators.v')
%%
% <<../verilog_operators.v.png>>
%% Import Verilog File
% To import the HDL file and generate the Simulink(TM)  model, pass the file 
% name as a character vector to the |importhdl| function.
importhdl('VerilogOperators.v')
%%
% HDL import parses the input file and displays messages of the import process 
% in the MATLAB(TM) Command Window. The import provides a link to the generated 
% Simulink(TM)  model |VerilogOperators.slx|. The generated model uses the same
% name as the top module in the input Verilog file.
%% Examine Generated Simulink(TM) Model
% To open the generated Simulink(TM)  model, select the link. 
% The model is saved in the |hdlimport/VerilogOperators| path relative to the current folder.
% You can simulate the model and observe the simulation results.
addpath('hdlimport/VerilogOperators')
open_system('VerilogOperators.slx')
sim('VerilogOperators.slx')