%% Generate Simulink Model From Verilog Files with BlackBox Modules
% This example shows how you can import multiple files containing Verilog code 
% and generate the corresponding Simulink(TM) model. When you import
% multiple files, if you want to obfuscate the HDL code or if your files
% contain HDL code for vendor-specific IPs, you can import the HDL code as a 
% BlackBox module using the |importhdl| function.

% Copyright 2018 The MathWorks, Inc.

%% Specify input Verilog Files
% Make sure that the input HDL files do not contain any syntax errors, are 
% synthesizable, and use constructs that are supported by HDL import. For example, 
% this code shows three Verilog files that use module instantiation to form a 
% hierarchical design. One module |sequentialexp.v| implements a simple sequential 
% circuit based on an if-else condition. The other module |comditionalcomb.v| 
% implements a simple combinational arithmetic expression. 
edit('conditionalcomb.v')
edit('sequentialexp.v')
edit('intelip.v')
%%
% <<../seq_comb.v.png>>
%%
% See that the |sequentialexp.v| module instantiates an Intel(R) IP that 
% implements a single-precision floating-point adder.
%
% <<../intelipmodule.v.png>>
%
% A top module |top| contained in file |blackboxtop.v| instantiates the two modules
% in |conditionalcomb.v| and |sequentialexp.v|
edit('blackboxtop.v')
%%
% <<../blackboxtopmodule.v.png>>
%% Import Verilog Files
% To import the HDL file and generate the Simulink(TM) model, pass the file names 
% as a cell array of character vectors to the |importhdl| function. By default, 
% HDL import identifies the top module and clock bundle when parsing the input file. 
importhdl({'blackboxtop.v','conditionalcomb.v','sequentialexp.v','intelip.v'}, ... 
                            'topModule','top','blackBoxModule','intelip')
%%
% HDL import parses the input file and displays messages of the import process 
% in the MATLAB(TM) Command Window. The import provides a link to the generated 
% Simulink(TM)  model |top.slx|. The generated model uses the same
% name as the top module that is contained in the input Verilog file |conditionalcomb.v|.
%% Examine Generated Simulink(TM) Model
% To open the generated Simulink(TM) model, select the link. 
% The model is saved in the |hdlimport/top| path relative to the current folder.
% You can simulate the model and observe the simulation results.
addpath('hdlimport/top')
open_system('top.slx')
set_param('top','SimulationCommand','update')
%%
% To avoid a division by zero, you can suppress the warning diagnostic before simulation.
Simulink.suppressDiagnostic({'top/top/u_seq/Div'}, ...
                                'SimulinkFixedPoint:util:fxpDivisionByZero')
sim('top')
%%
% You can see the hierarchy of Subsystems that implement the Verilog code
% that uses module instantiation.
open_system('top/top/u_comb')
%%
% If you open the Subsystem that implements the sequential circuit, you can
% open the |u_intelip| Subsystem to see the blackbox implementation.
open_system('top/top/u_seq')
%%
open_system('top/top/u_seq/u_intelip')