%% Generate Simulink Model From Multiple Verilog Files with Combinational and Sequential Logic
% This example shows how you can import multiple files containing Verilog code
% and generate the corresponding Simulink(TM) model.

% Copyright 2018 The MathWorks, Inc.

%% Specify input Verilog File
% Make sure that input HDL files do not contain any syntax errors, are
% synthesizable, and use constructs that are supported by HDL import. For example,
% this code shows three Verilog files that use module instantiation to form a
% hierarchical design. One module |example1.v| implements a simple sequential
% circuit based on an if-else condition. The other module |example2.v| implements a
% simple combinational arithmetic expression. Make sure that the
% combination logic only uses blocking assignments and the sequential logic
% only uses nonblocking assignments.
edit('example1.v')
edit('example2.v')
%%
% <<../example.v.png>>
%%
% A top module contained in file |example.v| instantiates the two modules
% in |example1.v| and |example2.v|
edit('example.v')
%%
% <<../example_top.v.png>>
%% Import Verilog Files
% To import the HDL file and generate the Simulink(TM) model, pass the file names
% as a cell array of character vectors to the |importhdl| function. By default,
% HDL import identifies the top module and clock bundle when parsing the input file.
importhdl({'example.v','example1.v','example2.v'})
%%
% HDL import parses the input file and displays messages of the import process
% in the MATLAB(TM) Command Window. The import provides a link to the generated
% Simulink(TM) model |example.slx|. The generated model uses the same
% name as the top module that is contained in the input Verilog file |example1.v|.
%% Examine Generated Simulink(TM) Model
% To open the generated Simulink(TM) model, select the link.
% The model is saved in the |hdlimport/example| path relative to the current folder.
% You can simulate the model and observe the simulation results.
addpath('hdlimport/example')
open_system('example.slx')
%%
% To avoid a division by zero, you can suppress the warning diagnostic before simulation.
Simulink.suppressDiagnostic({'example/example/example2/Div'}, ...
'SimulinkFixedPoint:util:fxpDivisionByZero');
set_param('example', 'IntegerOverflowMsg', 'None');
sim('example');
%%
% You can see the hierarchy of Subsystems that implement the Verilog code
% that uses module instantiation.
open_system('example/example/example1')
%%
open_system('example/example/example2')