%% Description
% This issue occurs when your Simulink(TM) model has a significantly large
% difference in sample rates or uses certain block implementations or optimizations 
% that result in different clock-rate paths, such as:
%
% * Multicycle block implementations
% * Input and output pipelining
% * Distributed pipelining
% * Floating-point library mapping
% * Native floating-point HDL code generation
% * Fixed-point math functions such as reciprocal, sqrt, or divide
% * Resource sharing
% * Streaming
%
% The additional pipelines result in a latency overhead that requires the
% insertion of matching delays across multiple signal paths operating at different rates. 
% If the ratio of the fastest to the slowest clock rate is quite large, 
% the code generator can potentially introduce a large number of registers in the 
% resulting HDL code. The large number of pipeline registers can increase
% the size of the generated HDL files, and can prevent the design from fitting
% into an FPGA.
%%
% To see an example of how this issue occurs, open this Simulink(TM) model.
open_system('hdlcoder_multirate_high_differential')
%%
% When you compile the model and double-click the |hdlcoder_multirate_high_differential| 
% Subsystem, you can see that the model has a floating-point Gain block, a 
% multicycle operator, in the fast clock-rate region.
%
% <<../hdlcoder_high_rate_diff.png>>
%
% Generate HDL code for the |hdlcoder_multirate_high_differential| Subsystem and
% check the output log.
%
% <<../hdlcoder_makehdl_high_rate_diff.png>>
%%
% Open the generated model. At the command line, enter |gm_hdlcoder_multirate_high_differential|.
% When you compile the model and double-click the
% |hdlcoder_multirate_high_differential| Subsystem, the model looks as
% displayed by the sample time legend.
%
% <<../hdlcoder_gm_high_rate_diff.png>>
%
% The large output latency on the fast clock rate region of the design is
% introduced by the code generator to balance delays across multiple output 
% paths of the system. This large latency increases the size of the generated 
% HDL files and reduces the efficiency of the generated code.

%% 
% Copyright 2012 The MathWorks, Inc.