%% Create and Customize Floating Point Configuration and Generate Code
% This example shows how to create a floating-point target configuration
% with Altera(R) Megafunctions (ALTFP) in HDL Coder, and then generate code.
%% Create a Floating-Point Target Configuration
% To create a floating-point configuration, use 
% hdlcoder.createFloatingPointTargetConfig. Before creating a configuration, 
% set up the path to your synthesis tool.
hdlsetuptoolpath('ToolName', 'Altera Quartus II', ...
    'ToolPath', 'C:/Altera/16.0/quartus/bin64/quartus.exe');
load_system('sfir_single')
fpconfig = hdlcoder.createFloatingPointTargetConfig('ALTFP')

%% Specify Custom Library Settings
% Optionally, to customize the floating-point configuration, 
% specify custom library settings. 
fpconfig.LibrarySettings.LatencyStrategy = 'MAX';
fpconfig.LibrarySettings.Objective = 'AREA';
fpconfig.LibrarySettings

%% View Latency of Floating-Point IPs
% The IPConfig object displays the maximum amd minimum latency values of
% the floating-point operators.
fpconfig.IPConfig

%% Customize Latency of ADDSUB IP
% Using the customize method of the IPConfig object, you can customize the
% latency of the floating-point IP and specify any additional arguments.
fpconfig.IPConfig.customize('ADDSUB','Single','Latency',6);
fpconfig.IPConfig

%% Generate Code
makehdl('sfir_single/symmetric_fir','FloatingPointTargetConfiguration',fpconfig, ...
        'TargetDirectory','C:/FloatingPoint/hdlsrc','SynthesisToolChipFamily','Arria10')
                
%%
% The latency of the ADDSUB IP is 6 and not the maximum latency value of 14.
% 
% The generated VHDL code is saved in the |hdlsrc| folder.

%% 
% Copyright 2012 The MathWorks, Inc.